International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Digital arithmetic plays an important role in the design of general-purpose digital processors and of embedded systems for signal processing, graphics, and communications. In spite of a mature body of knowledge in digital arithmetic, each new generation of processors or digital systems creates new arithmetic design problems. Designers, researchers, and graduate students will find solid solutions to these problems in this comprehensive, state-of-the-art exposition of digital arithmetic. Ercegovac and Lang, two of the field's leading experts, deliver a unified treatment of digital arithmetic, tying underlying theory to design practice in a technology-independent manner. They consistently use an algorithmic approach in defining arithmetic operations, illustrate concepts with examples of designs at the logic level, and discuss cost/performance characteristics throughout. Students and practicing designers alike will find Digital Arithmetic a definitive reference and a consistent teaching tool for developing a deep understanding of the "arithmetic style" of algorithms and designs. Guides readers to develop sound solutions, avoid known mistakes, and repeat successful design decisions. Presents comprehensive coveragefrom fundamental theories to current research trends. Written in a clear and engaging style by two masters of the field. Concludes each chapter with in-depth discussions of the key literature. Includes a full set of over 250 exercises, an on-line appendix with solutions to one-third of the exercises and 600 lecture slides

Digital arithmetic

Augmented Reality (AR) technologies for supporting maintenance operations have been an academic research topic for around 50 years now. In the last decade, major progresses have been made and the AR technology is getting closer to being implemented in industry. In this paper, the advantages and disadvantages of AR have been explored and quantified in terms of Key Performance Indicators (KPI) for industrial maintenance. Unfortunately, some technical issues still prevent AR from being suitable for industrial applications. This paper aims to show, through the results of a systematic literature review, the current state of the art of AR in maintenance and the most relevant technical limitations. The analysis included filtering from a large number of publications to 30 primary studies published between 1997 and 2017. The results indicate a high fragmentation among hardware, software and AR solutions which lead to a high complexity for selecting and developing AR systems. The results of the study show the areas where AR technology still lacks maturity. Future research directions are also proposed encompassing hardware, tracking and user-AR interaction in industrial maintenance is proposed.

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A systematic review of augmented reality applications in maintenance

Flow visualization has been a very attractive component of scientific visualization research for a long time. Usually very large multivariate datasets require processing. These datasets often consist of a large number of sample locations and several time steps. The steadily increasing performance of computers has recently become a driving factor for a reemergence in flow visualization research, especially in texture-based techniques. In this paper, dense, texture-based flow visualization techniques are discussed. This class of techniques attempts to provide a complete, dense representation of the flow field with high spatio-temporal coherency. An attempt of categorizing closely related solutions is incorporated and presented. Fundamentals are shortly addressed as well as advantages and disadvantages of the methods.

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The State of the Art in Flow Visualization : Dense and Texture-Based Techniques

Many algorithms have been developed for implementing division in hardware. These algorithms differ in many aspects, including quotient convergence rate, fundamental hardware primitives, and mathematical formulations. The paper presents a taxonomy of division algorithms which classifies the algorithms based upon their hardware implementations and impact on system design. Division algorithms can be divided into five classes: digit recurrence, functional iteration, very high radix, table look-up, and variable latency. Many practical division algorithms are hybrids of several of these classes. These algorithms are explained and compared. It is found that, for low-cost implementations where chip area must be minimized, digit recurrence algorithms are suitable. An implementation of division by functional iteration can provide the lowest latency for typical multiplier latencies. Variable latency algorithms show promise for simultaneously minimizing average latency while also minimizing area.

Division algorithms and implementations

The Q-Coder algorithm is a very efficient compression technique for bi-level images based on the arithmetic coding. The paper presents a new and fast version of the Q-Coder algorithm in which the carry-propagated adders have been replaced by carry-save adders. In this way, all the additions can be performed with a delay time of a single fill adder, independently of the length of the operands. The compression method is faster than the traditional Q-Coder algorithm with an almost unnoticeable increasing of the hardware requirements.

A Q-Coder algorithm with carry free addition

The authors present a parallel algorithm for fast rendering. A set of zones which can be concurrently processed is identified; this set is split into a number of subsets equal to the number of available processors. Each processor renders, in parallel with the others, a zone of its set.

Parallel algorithm for image rendering and its implementation

A general approach is outlined for designing units for higher radix division, which are based on two subunits operating in parallel. A lower radix division unit is used as the building block of the architecture, and the division step is split into two phases which are carried out in parallel. It is shown that the proposed architecture permits the design of units for higher radix division with digit selection tables requiring few supplementary input bits compared to the tables used by lower radix division systems. >

On the implementation of a parallel algorithm for higher radix division

A class of systolic architectures designed to evaluate bicubical parametric polynomials for a set of fixed and uniformly spaced values of the two parameters is presented. The arrays fit very well into a more general context in which special units are designed to convert the description of an object given in terms of parametric surfaces into a representation which is more convenient for the rendering algorithm, for example, ray tracing and ray casting. It can be demonstrated that a surface can be represented by means of a set of 'surface patches', each one defined by means of a given set of control vertices. Three bicubical polynomials (one for each spatial coordinate) define each surface patch. The proposed hardware solution does not require dividers, but only shifters. The evaluation process produces 81 results for each polynomial, since a matrix of 9*9 different pairs of values of the parameters (u,v) has to be considered. >

Systolic arrays for bicubical polynomial evaluation in computer graphics

This installment of Computer’s series highlighting the work published in IEEE Computer Society journals comes from IEEE Transactions on Computers.

Paolo Montuschi

Papers

A Q-Coder algorithm with carry free addition

Parallel algorithm for image rendering and its implementation

On the implementation of a parallel algorithm for higher radix division

Systolic arrays for bicubical polynomial evaluation in computer graphics

The Rise of Hardware Security in Computer Architectures