Envelope-tracking common-drain CMOS power amplifier with a switching-only supply modulator for LTE applications

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna's 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3---60.7%.

Design of efficient power amplifier for low power transmitters

In this paper, we propose a novel topology for an injection locked differential power amplifier. This power amplifier is targeted for low power wireless applications such as ZigBee at 2.4GHz band. This topology involving body injection locking for higher efficiency is designed in TSMC 65nm RF-CMOS process and it achieves a Power added efficiency of 61.8% and a Drain efficiency of 63.6% with an output power level of 12.3dBm at a supply voltage of 0.5V. General theory of injection locking has been discussed before presenting our topology. Reasons have also been presented to justify the adoption of body injection locking to improve the efficiency.

A High Efficiency Body Injected Differential Power Amplifier at 2.4GHz for Low Power Applications

Analysis and improvement of PSRR in an envelope‐tracking power amplifier using a common‐drain amplifier topology

In this paper, a power amplifier implemented with a common-drain structure is introduced. With proper input matching, this structure is shown to provide a reasonable power gain and superior linearity and efficiency in comparison to other low-power topologies. This is shown to be due to the low dependency of the power gain to the transistor transconductance and the low-voltage variations across the gate-source capacitance. This power amplifier is suitable for low-power and short-range applications such as Bluetooth Low Energy (BLE). Based on the calculated S-parameters, the operation frequency of this amplifier and its design trade-offs are presented, along with a comparison with competitive topologies. The design is simulated in a 0.13 μm CMOS technology, operates with a 1.2 V supply, and provides a power gain of 8.5 dB with a DC power consumption of 3.6 mW. The input 1-dB compression point is 2.2 dBm, yielding a power added efficiency of 43%.

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Parvaneh Saffari

Papers

Low-energy CMOS common-drain power amplifier for short-range applications