Map-matching is the process of aligning a sequence of observed user positions with the road network on a digital map. It is a fundamental pre-processing step for many applications, such as moving object management, traffic flow analysis, and driving directions. In practice there exists huge amount of low-sampling-rate (e.g., one point every 2--5 minutes) GPS trajectories. Unfortunately, most current map-matching approaches only deal with high-sampling-rate (typically one point every 10--30s) GPS data, and become less effective for low-sampling-rate points as the uncertainty in data increases. In this paper, we propose a novel global map-matching algorithm called ST-Matching for low-sampling-rate GPS trajectories. ST-Matching considers (1) the spatial geometric and topological structures of the road network and (2) the temporal/speed constraints of the trajectories. Based on spatio-temporal analysis, a candidate graph is constructed from which the best matching path sequence is identified. We compare ST-Matching with the incremental algorithm and Average-Frechet-Distance (AFD) based global map-matching algorithm. The experiments are performed both on synthetic and real dataset. The results show that our ST-matching algorithm significantly outperform incremental algorithm in terms of matching accuracy for low-sampling trajectories. Meanwhile, when compared with AFD-based global algorithm, ST-Matching also improves accuracy as well as running time.

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Map-matching for low-sampling-rate GPS trajectories

A system includes a computing device that selectively communicates with a self-powered device. The self-powered device has several modes of operation, including a first low-power mode of operation and a second high-power mode of operation. The self-powered device is to communicate with the computing device when the self-powered device is in the second mode of operation. The self-powered device may conserve power by alternating between the first mode of operation and the second mode of operation such that the self-powered device is in the second mode of operation during pre-determined or adaptively-determined time intervals. A duty-cycle of the second mode of operation relative to the first mode of operation may be in accordance with a power budget for the self-powered device.

Self-Powered Devices and Methods

Described is a technology by which raw GPS data is processed into segments of a trip, with a predicted mode of transportation (e.g., walking, car, bus, bicycling) determined for each segment. The determined transportation modes may be used to tag the GPS data with transportation mode information, and/or dynamically used. Segments are first characterized as walk segments or non-walk segments based on velocity and/or acceleration. Features corresponding to each of those walk segments or non-walk segments are extracted, and analyzed with an inference model to determine probabilities for the possible modes of transportation for each segment. Post-processing may be used to modify the probabilities based on transitioning considerations with respect to the transportation mode of an adjacent segment. The most probable transportation mode for each segment is selected.

Learning transportation modes from raw gps data

A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

Power managers for an integrated circuit

Sensor platforms and methods of making them are described, and include platforms having horizontally oriented sensor elements comprising nanotubes or other nanostructures, such as nanowires. Under certain embodiments, a sensor element has an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes, and, under certain embodiments, it comprises derivatized or functionalized nanotubes. Under certain embodiments, a sensor is made by providing a support structure; providing a collection of nanotubes on the structure; defining a pattern within the nanotube collection; removing part of the collection so that a patterned collection remains to form a sensor element; and providing circuitry to electrically sense the sensor's electrical characterization. Under certain embodiments, the sensor element comprises pre-derivatized or pre-functionalized nanotubes. Under certain embodiments, sensor material is derivatized or functionalized after provision on the structure or after patterning. Under certain embodiments, a large-scale array includes multiple sensors.

Sensor platform using a non-horizontally oriented nanotube element

An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of the integrated circuit. Special power control instructions are added to user applications in order to control via the power control unit, the power consumption of the different functional units.

Managing VT for reduced power using power setting commands in the instruction stream

According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode

In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

Method and apparatus for reducing power consumption in VLSI circuit designs

A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

Stacked voltage rails for low-voltage DC distribution

A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.

Patrick E. Perry

Papers

Managing VT for reduced power using power setting commands in the instruction stream

Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode

Method and apparatus for reducing power consumption in VLSI circuit designs

Stacked voltage rails for low-voltage DC distribution

Control of multiple equivalent functional units for power reduction