We introduce and analyze a new family of multiprocesser interconnection networks, called generalized fat trees, which include as special cases the fat trees used for the connection machine architecture CM-5, pruned butterflies, and various other fat trees proposed in the literature. The generalized fat trees provide a formal unifying concept to design and analyse a fat tree based architecture. The extended generalized fat tree network XGFT(h; m/sub 1/, ..., m/sub h/; w/sub 1/, ..., w/sub h/) of height h has /spl Pi//sub i=1//sup h/ m/sub i/ leaf processors and the inner nodes serve only as switches or routers. Each non-leaf node in level i has m/sub i/ children and each non-root has w/sub i+1/ parent nodes. The generalized fat trees provide regularity, symmetry, recursive scalability, maximal fault-tolerance, logarithmic diameter bisection scalability, and permit simple algorithms for fault tolerant self-routing and broadcasting. These networks are also versatile, since they can efficiently embed rings, meshes and tori, trees, pyramids and hypercubes. >

On generalized fat trees

Universality in VLSI Computation

A quantitative comparison of the BSP and LogP models for parallel computation is developed. Very efficient cross simulations between the two models are derived, showing their substantial equivalence for algorithmic design guided by asymptotic analysis. It is also shown that the two models can be implemented with similar performance on most point-to-point networks. In conclusion, within the limits of our analysis that is mainly of asymptotic nature, BSP and LogP can be viewed as closely related variants within the bandwidth-latency framework for modeling parallel computation. BSP seems somewhat preferable due to greater simplicity and portability, and slightly greater power.

BSP vs LogP

Horizons of parallel computation

Currently known parallel communication schemes allow n nodes interconnected by arcs (in such a way that each node meets only a fixed number of arcs) to transmit n packets according to an arbitrary permutation in such a way that (1) only one packet is sent over a given arc at any step, (2) at most 0(log n) packets reside at a given node at any time and (3) with high probability, each packet arrives at its destination within 0(log n) steps. We present and analyze a new parallel communication scheme that ensures that at most a fixed number of packets reside at a given node at any time.

Parallel Communication with Limited Buffers (Preliminary Version)

Two deterministic routing networks are presented: the pruned butterfly and the sorting fat-tree. Both networks are area-universal, that is, they can simulate any other routing network fitting in similar area with polylogarithmic slowdown. Previous area-universal networks were either for the off-line problem, where the message set to be routed is known in advance and substantial precomputation is permitted, or involved randomization, yielding results that hold only with high probability. The two networks introduced here are the first that are simultaneously deterministic and on-line, and they use two substantially different routing techniques. The performance of their routing algorithms depends on the difficulty of the problem instance, which is measured by a quantity l known as the load factor. The pruned butterfly runs in time O(llog2N), is the number of possible sources and destinations for messages and l is assumed to be polynomial in N. The sorting fat-tree algorithm runs in O(l log N + log2N) time for a restricted class of message sets including partial permutations. Other results of this work include a “flexible” circuit that is area-time optimal across a range of different input sizes and an area-time lower bound for routers based on wire-length arguments.

/pdf/deterministic-on-line-routing-on-area-universal-networks-1mstkcgcwb.pdf

Deterministic on-line routing on area-universal networks

Two deterministic routing networks, the pruned butterfly and the sorting fat-tree, are presented. Both networks are area universal, i.e. they can simulate with polylogarithmic slowdown, any other routing network fitting in similar area. Previous area-universal networks were either for the offline problem, where the message set to be routed is known in advance and substantial precomputation is permitted, or involved randomization, yielding results that hold only with high probability. The present networks are the first that are simultaneously deterministic and online, and they use two substantially different routing techniques. The performance of the routing algorithms depends on the difficulty of the problem instance, which is measured by a quantity lambda , known as the load factor. The pruned butterfly algorithm runs in time O( lambda log/sup 2/N), where N is the number of possible sources and destinations for messages and lambda is assumed to be polynomial in N. The sorting fat-free algorithm runs in O( lambda log N + log/sup 2/N) time for a restricted class of message sets, including partial permutations. Other results include a new type of sorting circuit, an area universal circuit, and an area-time lower bound for routers. >

/pdf/deterministic-on-line-routing-on-area-universal-networks-2rd8q82488.pdf

An area-universal VLSI circuit

A graph-theoretic definition is proposed to make precise the sense in which a “fat-tree” is a tree-like interconnection of subnetworks whose bandwidth is adequately described by the capacity of the channels between subnetworks. The definition is shown to encompass a number of known networks such as the concentrator fat-tree, the pruned butterfly, and the tree-of-meshes. In the established framework, a non-trivial Ω(N log2N) lower bound is derived for the area of a class of fat-trees, with implications for their area-universality.

An Area Lower Bound for a Class of Fat-Trees (Extended Abstract)

We present two deterministic routing networks, the pruned butterfly and the sorting fat-tree. Both networks are area-universal, i.e., they can simulate any other routing network fitting in similar area with polylogarithmic slowdown. Previous area-universal networks were either for the off-line problem, where the message set to be routed is known in advance and substantial precomputation is permitted, or involved randomization, yielding results that hold only with high probability. Our two networks are the first that are simultaneously deterministic and on-line, and they use two substantially different routing techniques. The performance of our routing algorithms depends on the difficulty of the problem instance, which is measured by a quantity X known as the load factor. The pruned butterfly algorithm runs in time O(X log' N), where N is the number of possible sources and destinations for messages and X is assumed to be polynomial in N. The sorting fat-tree algorithm runs in O(X log N + log2 N) time for a restricted class of message sets including partial permutations. Other results of this work include a new type of sorting circuit, an area-universal circuit, and an area-time lower bound for routers.

Paul Bay

Papers

Deterministic on-line routing on area-universal networks

Deterministic on-line routing on area-universal networks

An area-universal VLSI circuit

An Area Lower Bound for a Class of Fat-Trees (Extended Abstract)

Deterministic On-Line Routing on Area-Universal Networks* (Extended Abstract)