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Deterministic on-line routing on area-universal networks

Paul Bay, +1 more
- pp 297-306
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TLDR
The present networks are the first that are simultaneously deterministic and online, and they use two substantially different routing techniques, including a new type of sorting circuit, an area universal circuit, and an area-time lower bound for routers.
Abstract
Two deterministic routing networks, the pruned butterfly and the sorting fat-tree, are presented. Both networks are area universal, i.e. they can simulate with polylogarithmic slowdown, any other routing network fitting in similar area. Previous area-universal networks were either for the offline problem, where the message set to be routed is known in advance and substantial precomputation is permitted, or involved randomization, yielding results that hold only with high probability. The present networks are the first that are simultaneously deterministic and online, and they use two substantially different routing techniques. The performance of the routing algorithms depends on the difficulty of the problem instance, which is measured by a quantity lambda , known as the load factor. The pruned butterfly algorithm runs in time O( lambda log/sup 2/N), where N is the number of possible sources and destinations for messages and lambda is assumed to be polynomial in N. The sorting fat-free algorithm runs in O( lambda log N + log/sup 2/N) time for a restricted class of message sets, including partial permutations. Other results include a new type of sorting circuit, an area universal circuit, and an area-time lower bound for routers. >

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References
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Fat-trees: universal networks for hardware-efficient supercomputing

TL;DR: In this article, the authors presented a new class of universal routing networks, called fat-trees, which might be used to interconnect the processors of a general-purpose parallel supercomputer, and proved that a fat-tree of a given size is nearly the best routing network of that size.
Journal ArticleDOI

Access and Alignment of Data in an Array Processor

TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Journal ArticleDOI

Fat-trees: Universal networks for hardware-efficient supercomputing

TL;DR: In this article, the authors presented a new class of universal routing networks, called fat-trees, which might be used to interconnect the processors of a general-purpose parallel supercomputer, and proved that a fat-tree of a given size is nearly the best routing network of that size.
Proceedings ArticleDOI

Universal schemes for parallel communication

TL;DR: This paper shows that there exists an N-processor computer that can simulate arbitrary N- processor parallel computations with only a factor of O(log N) loss of runtime efficiency, and isolates a combinatorial problem that lies at the heart of this question.
Proceedings ArticleDOI

An 0(n log n) sorting network

TL;DR: A sorting network of size 0(n log n) and depth 0(log n) is described, and a derived procedure (&egr;-nearsort) are described below, and the sorting network will be centered around these elementary steps.