Showing papers by "Paul Jespers published in 1977"

A fast sample and hold charge-sensing circuit for photodiode arrays

Abstract: An on-chip charge-sensing circuit with a feedback loop has been designed for improving the charge-transfer speed in photodiode arrays. Its large output voltage swing combined with improved speed performances, makes this circuit well-suited for OCR applications, especially low-cost data capture devices. Sample and hold operation can easily be performed without increasing the Si real estate, making parallel output feasible with frame rates of 3 kHz for arrays with 500 pixels. Experimental arrays were built in standard p-channel aluminum-gate technology.

Three-terminal CID as random access memory cell

Abstract: A method for electrical write-in via punchthrough is described, with which CIDs can be operated as memories The principle has been successfully proven on a 3T-CID RAM Estimated values achievable with an optimized device are presented

Process and device modeling for integrated circuit design : [proceedings of the NATO Advanced Study Institute on Process and device modeling for integrated circuit design, Louvain-la-Neuve, Belgium, July 19-29, 1977]

Abstract: An Advanced Study Institute on process and device modeling for integrated circuit design was held in Louvain-la-Neuve. Belgium on July 19-29. 1977 under the auspices of the Scientific Affairs Division of NATO. The Institute was organized by a scientific organizing committee consisting of Professor F. Van de Wiele of the Universite Catholique de Louvain. Professor W. L. Engl of the Technische Hochschule Aachen and Professor P. Jespers of the Universite Catholique de Louvain. This book represents the contributions of the lecturers at the Institute and the chapters present a concise treatment of a very timely subject. namely. process and device modeling for integrated circuit design. The organization of the book parallels the program at the Institute with an introd0ction .comprised of a review of mo deling and basic semiconductor physics. This is followed by the chapters devoted to basic technologies. modeling of bipolar and MoS devices. The last chapter of the book presents the specific topic of process modeling. The subject matter of this book is suitable for a wide range of interests from the advanced student. through the practisihg physicist and engineer. to the research worker. Although a novice may find some difficulty with the mathematical development. he can acquire a perspective into the field of process and device modeling for integrated circuit design with this bDOk. Likewise. portions of this book may be used as a textbook since the chap ters are intructional and self-contained."

Cell Three-Terminal CID as Random Access Memory

Abstract: The total area of the active circuit is 400 urn X 225 #m without layout optimization. An optimum design using the same layout rules and parallel collector structures would result in an area of about 270 pm X 90 #m. The corresponding area for a binary 12L full adder fabricated using the same technology and layout rules and perpendicular collector structures was crdculated to be 290 m X 120 pm. This implies that an opY timized multivalued I L full adder circuit occupies 70 percent of the area of the binary full adder. If the multivrdued 12L full adder is constructed usihg perpendicular collector structures, a further reduction in area would result. The 12L threshold gates were characterized by measuring 6P and &. A curve tracer was used for the measurements. The typical value of PMwas 3 for collector currents ranging from 20 to 200 PA. In the same range of currents, thle value of & was 600. The beta matching for a set of three collectors in a parallel structure with a unity area injector was found to be better than 3 percent over a range of current from 10 pA to 1 mA. The collector-to-emitter breakdown voltage for the upside-down n-p-n transistor was 1.6 V. The full adder operation was successfully tested at low frequency using three synchronized input signals applied to terminals Xl , X2, and Cl. A TTL-to-12 L interface consisting of a single inverter stage was used at the input and an 12L-toTTL interface consisting of two inverters in series was used at the output. The speed of operation of the circuit was tested with a stable dc level corresponding to a “one” at the Xl input, a stable dc level corresponding to a “zero” at the X2 input, and a pulse applied to the Cl input. The delays of the sum and carry outputs are t~~= 1.5 ps and tjc= 0.9 ps, respectively, at an injector current of 75 IA. These delays include the delays of the input and output interfaces. The intrinsic values of the delays without the interfaces are td$ = 1.2 us and td~= 0.6 #s. In the multilevel full adder, all three inputs are interchangeable and the resultant delay is the same for any combination of a dc “zero” input, a dc “one” input, and a pulsed input. For compwison purposes, the corresponding intrinsic sum delay for a binary full adder operated at the same injection current and using the same interfaces was found to be approximately 0.8 p.s. In the case of thle binary full adder, all three inputs are not directly interchangeable and the delay depends on whether one of the inputs o.r the carry is clocked. The value 0.8 ps for the delay was obtained by averaging the delays for the case of a dc “zero” input, a dc “one” input, and a clocked carry and the case of a dc “zero” input, a clocked input, and a dc “one” carry. Therefore, it appears that for the same power dissipation, the area x delay product (in this case the delay refers to the delay associated with the sum output) for the multivalued full adder is approximately the same as for the binary full adder. CONCLUSION The multivalued full adder implemented using 12 L technology offers a sizable reduction in area while operating at approximately the same area x delay product as the binary version. The logic scheme described in this correspondence can be applied to the realization of a variety of other logic functions and, furthermore, (can be extended to levels higher than four with improvements in processing technology.