A method for forming an Al layer using an atomic layer deposition method is disclosed. First, a semiconductor substrate is loaded into a deposition chamber. Then, an Al source gas is supplied into the deposition chamber and the Al source gas is chemisorbed into the semiconductor substrate to form the Al layer. Next, a purge gas is supplied onto the deposition chamber without supplying the Al source gas so that the unreacted Al source gas is removed, thereby completing the Al layer. To form an Al layer to a required thickness, the step of supplying the Al source gas and the step of supplying the purge gas are repeatedly performed, thereby forming an Al atomic multilayer. Therefore, the uniformity and step coverage of the Al layer can be greatly improved.

Method for manufacturing aluminum metal interconnection layer by atomic layer deposition method

An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material

High-performance cmos soi device on hybrid crystal-oriented substrates

A process for preparing a polycrystalline semiconductor thin film transistor wherein a non-singlecrystalline semiconductor formed on a transparent insulating substrate is annealed by laser beams, such process comprising forming a gate insulation layer and a gate electrode on the non-singlecrystalline semiconductor; implanting impurity ions into a source-drain region of the semiconductor wherein the gate electrode is used as a mask, and irradiating laser beams from the rear surface side of the transparent insulating substrate to thereby polycrystallize the non-singlecrystalline semiconductor under the gate electrode or improve the crystallinity of the semiconductor without causing the non-singlecrystalline semiconductor in a completely molten state.

Process for preparing a polycrystalline semiconductor thin film transistor

An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 μm or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral portions) of the island semiconductor regions, at least a portion used to form a channel of a thin film transistor (TFT), or a portion that a gate electrode crosses is etched, so that a region that the distortion is accumulated is removed. By using such semiconductor regions, a TFT is produced.

Method for producing insulated gate thin film semiconductor device

A method for producing a semiconductor film comprising steps of: preparing a first substrate and a second substrate; superposing the first substrate on the second substrate to form an assembly of combined substrates; applying energy to the assembly of combined substrates to melt a portion within the assembly to form a molten portion therein; cooling the molten portion to crystallize the portion to form a single crystal structure therein; and separating the first substrate from the second substrate. The method makes it possible to control the crystal axis orientation of the recrystallized single crystal structure.

Method for producing semiconductor film

A method for trench isolation of a silicon island for device fabrication using only conventional very large scale integration (VLSI) techniques is provided. The combination of the sidewall isolation achieved with the trench isolation and the underlying oxide film create a totally dielectrically isolated structure without the possibility of latch-up between adjacent devices.

Trench isolated transistors in semiconductor films

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2- mu m emitter-base polysilicon contact separation. A 0.4- mu m emitter width is achieved with conventional 0.8- mu m optical lithography. Scaling of the emitter width of 0.3 mu m has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 mu m has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f/sub t/ as high as 33.8 GHz. >

A high-speed bipolar technology featuring self-aligned single-poly base and submicrometer emitter contacts

Regular arrays of grain boundary free silicon islands have been produced in a silicon on insulator (SOI) structure by using a pattern antirelfective coating in combination with a laser scanning technique. The antireflective coating pattern is made up of a series of parallel stripes terminating in seeding windows. A laser beam is scanned perpendicular to the stripes and over at least two stripes simultaneously, with the long axis of the beam parallel to the scan direction. Grain boundaries are confined to the region under the antireflective stripes.

Grain boundary confinement in silicon-on-insulator films

Insufficient short-circuit (SC) robustness of currently commercial GaN power devices, i.e., the high electron mobility transistors (HEMTs), is a key roadblock for their applications in automotive powertrains. At a 400 V bus voltage (<italic>V</italic>BUS), the SC withstanding time (<italic>t</italic>SC) of commercial GaN HEMTs is typically below 1 μs, far below the usual system requirement (>10 μs). This letter presents breakthrough short-circuit capability in a vertical GaN fin-channel junction-gate field-effect transistor (Fin-JFET). The Fin-JFET is normally <sc>off</sc> with a 0.7 mΩ·cm2 specific <sc>on</sc>-resistance and 800 V avalanche breakdown voltage (BVAVA) at the room temperature. The gate driver in the short-circuit test was designed to be identical to that in device switching applications. The <italic>t</italic>SC of GaN Fin-JFETs was measured to be 30.5 μs at a <italic>V</italic>BUS of 400 V, 17.0 μs at 600 V, and 11.6 μs at 800 V, all among the longest reported for 600–700 V normally <sc>off</sc> transistors. In addition, GaN Fin-JFETs failed open in these tests and retained BVAVA after failure, which is highly desirable for system applications. In the repetitive 10 <italic>μ</italic>s, 400 V short-circuit tests, GaN Fin-JFETs showed no degradation after 30 000 cycles. Furthermore, to the best of our knowledge, this is the first report of a power transistor with good short-circuit ruggedness at a bus voltage close to its BVAVA. The underlying mechanism is the unique avalanche-through-fin in the Fin-JFET, which is validated by mixed-mode TCAD simulations and unclamped inductive switching tests. These results reveal the inherent ruggedness of GaN Fin-JFETs in the concurrent presence of short-circuit and overvoltage in power electronics systems.

Breakthrough Short Circuit Robustness Demonstrated in Vertical GaN Fin JFET

The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normally off and has a specific on-resistance smaller than that of 1.2-kV SiC mosfets. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of power mosfets (via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a mosfet driver with a large gate resistance or an RC-interface driver. These drivers turn on the fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiC mosfets. Additionally, the RC-interface driver was shown to outperform the mosfet driver for vertical GaN JFETs. The learning about normally off GaN JFETs was applied to a study of commercial normally on SiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.

Clifford I. Drowley

Papers

Trench isolated transistors in semiconductor films

A high-speed bipolar technology featuring self-aligned single-poly base and submicrometer emitter contacts

Grain boundary confinement in silicon-on-insulator films

Breakthrough Short Circuit Robustness Demonstrated in Vertical GaN Fin JFET

Tuning Avalanche Path in Vertical GaN JFETs By Gate Driver Design