An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Emulation devices, systems and methods utilizing state machines

A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.

Processor condition sensing circuits, systems and methods

A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149.1 boundary scan architecture standard. Standard IEEE 1149.1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.

Technique for preconditioning I/Os during reconfiguration

A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the design via serial scan operations. The present invention allows a continuous scan path to be compressed or expanded so that the scan path only passes through the desired logic element(s) to be tested. Devices connected on the serial scan path (or ring) can be selected or deselected thus allowing the serial path to either flow through or bypass a given logic circuit's internal scan path. The invention can be used to create a hierarchical scan network consisting of a primary scan ring from which a multiplicity of scan sub-rings may be accessed.

Hierarchical scan selection

A method and system for reconstructing a relationship among events in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes controlling a mode of updating the at least one PMC through a bit set within the at least one MMCR, the bit set having a plurality of logic levels. Further included are determining if the bit set is at a first logic level, and placing the at least one PMC in a history mode if the bit set is at the first logic level.

Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system

A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n. Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.

Device for serializing/deserializing bit configurations of variable length

Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching an unoperational state detection task running on the n-1 priority level at time intervals smaller than a specified time-out delay. A detection timer (1) which is set at an initial value each time the task is dispatched and the content of which is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and which are reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request. Figure 2.

Device for improving detection of unoperational states in non-attended driven processor

Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching an unoperational state detection task running on the n-1 priority level at time intervals smallerthan a specified time-out delay. A detection timer (1) which is set at an initial value each time the task is dispatched and the content of which is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and which are reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request.

Paul Viallon

Papers

Device for serializing/deserializing bit configurations of variable length

Device for improving detection of unoperational states in non-attended driven processor

Device for improving the detection of non-operational states in a non-attended interrupt-driven processor

Series-parallel/parallel-series device for variable bit length configuration