Patent
Device for serializing/deserializing bit configurations of variable length
TLDR
A serdes device includes circuitry for loading or reading bit configurations into or out of strings of variable length nk+r, where n is the number of bits in a byte, k is the total number of bytes and r is the residual bits, with r being smaller than n.Abstract:
A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n. Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.read more
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References
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Patent
Device for loading and reading strings of latches in a data processing system
TL;DR: In this paper, a device for loading data in and reading data out of latch strings located in field replaceable units containing the circuitry of a data processing system realized in accordance with the Level-Scan Sensitive Design (LSSD) technique is described.
Patent
Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes
TL;DR: Eichelberger and Williams as discussed by the authors modified the known shift register latch (SRL) strategy by logically removing the master latch from the slave latch and providing the slave latches with multiple shift inputs, e.g., two shift inputs.
Patent
High speed shift register circuit
Masao Yamasawa,Soejima Tetsuo +1 more
TL;DR: A shift register circuit for converting a form of a datum with N bits comprises a shift register with a bit capacity of at least N+1 bits as discussed by the authors, each bit of the shift register is set so as to become a predetermined logic condition by a setting means.
Patent
Data processing system having auxiliary register storage
TL;DR: In this paper, the auxiliary storage element is capable of loading or being selectively loaded with information in its associated basic storage element, and means for logically interconnecting auxiliary storage elements to form a single shift register are provided.
Patent
Variable length shift register alternately operable to store and recirculate data and addressing circuit therefor
TL;DR: In this paper, a system for storing and thereafter cyclicly reproducing transient information including nm-element shift registers, either digital or analog, connected in cascade and operable in either (a) a data entry mode for storing transient data therein or (b) a recirculating mode for cyclically reproducing at the output thereof the information stored therein.