An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A mobile terminal including a body; a touchscreen provided to a front and extending to side of the body and configured to display content; and a controller configured to detect one side of the body comes into contact with one side of an external terminal, display a first area on the touchscreen corresponding to a contact area of the body and the external terminal and a second area including the content, receive an input of moving the content displayed in the second area to the first area, display the content in the first area, and share the content in the first area with the external terminal.

Mobile terminal and method for controlling the same

The aim of the disclosed invention is to provide a capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attains extremely low resistance and low inductance involved in connection between an IC chip and the capacitor and to provide a printed wiring substrate and a capacitor used in the same. To achieve this object, a capacitor-built-in-type printed wiring substrate (100) on which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrate (110) and an IC chip (101) mounted on the capacitor-built-in-type printed wiring substrate (110). A printed wiring substrate (120) includes a number of connection-to-IC substrate bumps (152) and a closed-bottomed capacitor accommodation cavity (121) formed therein. A capacitor (130) is disposed in the cavity (121) and includes a pair of electrode groups (133E and 133F) and a number of connection-to-IC capacitor bumps (131) connected to either one of the paired electrode groups (133E and 133F). The connection-to-IC capacitor bumps (131) are flip-chip-bonded to corresponding connection-to-capacitor bumps (103) on the IC chip. The connection-to-IC substrate bumps (152) are flip-chip-bonded to corresponding connection-to-substrate bumps (104) on the IC chip.

Capacitor-built-in-type printed wiring substrate, printed wiring substrate, and capacitor

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chips.

Integrated package and methods for making same

A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.

Semiconductor device and method of manufacturing the same, and electronic apparatus

A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Substrate interconnect for power distribution on integrated circuits

A flip-chip having a decoupling capacitor electrically coupled to the backside thereof The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface A plurality of raised bump contacts are located on the first surface and connected to the circuit elements A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects

Flip-chip having an on-chip decoupling capacitor

Micromachining techniques such as focused ion beam milling have become an integral part of the design debug cycle at many companies for providing fast verification of bug fixes in silicon. With flip chip packaging becoming more prevalent for future high performance processors, it is necessary to perform circuit edits and bug fixes on the silicon while the chip is packaged in the flip chip package. With this technology, however, conventional frontside probing and traditional circuit rewiring of packaged devices are not practical. We have developed a combination of new micromachining techniques for directly accessing metal signals from the backside of the chip. Here we will describe this new process, the technologies used, and some basic applications.

Application of advanced micromachining techniques for the characterization and debug of high performance microprocessors

A method and an apparatus for synchronizing a mode locked laser with a device under test. The present invention provides a stroboscopic technique that synchronizes the free running laser pulses of a mode locked laser to a DUT enabling the optical testing of integrated circuits to be performed and waveform measurements to be acquired from a DUT at random operating frequencies. In one embodiment, a laser synchronizing apparatus is configured to be used to test a device under test . The laser synchronizing apparatus includes a mode locked laser generating repeating laser pulses having a first period. A test pattern operating in M clocks when executed on the device under test is constructed. M is an integer and each one of the M clocks has a second period. A time per test pattern is computed such that the time per test pattern provides a sufficient amount of time to execute the constructed test pattern operating in the M clocks. The time per test pattern is a common multiple of the first period and the second period such that N laser pulses are generated during the time per test pattern with N being an integer. The test pattern is looped on the device under test with the laser synchronizing apparatus synchronized with the mode locked laser and each loop of the test pattern taking the time per test pattern to execute.

Method and apparatus for synchronizing a mode locked laser with a device under test

An apparatus is disclosed. In one embodiment, the apparatus includes a semiconductor substrate and a second substrate. The semiconductor substrate has a top side and a bottom side. The semiconductor substrate has an integrated circuit and at least one alignment fiducial formed on the top side. The alignment fudicial is aligned with the integrated circuit and the alignment fiducial is accessible from the bottom side. The semiconductor substrate further includes a first set of bond pads on the integrated circuit, the bond pads on the top side. The second substrate has a second set of bond pads corresponding to the first set of bond pads. The semiconductor substrate is coupled to the second substrate at a plurality of solder interconnections disposed between the first and the second set of bond pads.

Paul Winer

Papers

Substrate interconnect for power distribution on integrated circuits

Flip-chip having an on-chip decoupling capacitor

Application of advanced micromachining techniques for the characterization and debug of high performance microprocessors

Method and apparatus for synchronizing a mode locked laser with a device under test

Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate