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Paweł Tomaszewicz

Researcher at Warsaw University of Technology

Publications -  26
Citations -  188

Paweł Tomaszewicz is an academic researcher from Warsaw University of Technology. The author has contributed to research in topics: Field-programmable gate array & Logic synthesis. The author has an hindex of 7, co-authored 26 publications receiving 179 citations.

Papers
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Proceedings ArticleDOI

Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures

TL;DR: This paper presents an efficient method for implementation of digital filters targeted FPGA architectures and demonstrates that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.
Book ChapterDOI

5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs

TL;DR: It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs.
Book ChapterDOI

The Influence of Functional Decomposition on Modern Digital Design Process

TL;DR: The experimental results prove that functional decomposition as a method of synthesis can help implementing circuits in CPLD/FPGA architectures and can also be efficiently used as a methods for implementing FSMs in FPGAs with Embedded ROM Memory Blocks.
Journal ArticleDOI

Embedded Damage Localization Subsystem Based on Elastic Wave Propagation

TL;DR: Results of experimental verification of the developed damage localization algorithm as well as results of damage localization by the embedded subsystem are presented.
Proceedings Article

Logic synthesis strategy for FPGAs with embedded memory blocks

TL;DR: A logic synthesis method based on balanced decomposition that uses the concept of r-admissibility to efficiently utilize possibilities provided by memory blocks embedded in modern FPGA architectures is presented.