Thermal management and temperature uniformity enhancement of electronic devices by micro heat sinks: A review

Hotspot thermal management using a microchannel-pinfin hybrid heat sink

The efficient usage of thermoelectric (TE) devices for microelectronics cooling application requires investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances, and utilization of appropriate current pulses. We develop a computational model to investigate the effect of steady state and transient mode of operation of ultrathin thermoelectric cooler (TEC) devices on hot-spot cooling considering the effect of crucial thermal and electrical contact resistances. Our analysis shows that the transient pulses can be very effective in reducing the hot-spot temperature by 6-7°C in addition to the cooling achieved by the steady state current through the TEC device. We correlate the important characteristics of the transient temperature behavior of hot-spot under the TEC operation such as the maximum temperature drop (ΔTmax), time taken to achieve ΔTmax and temperature overshoot after turning off pulse current with the electrical and thermal contact resistances and Seebeck coefficient of the TE material. It has been observed that thermal and electrical contact resistances play a very crucial role in the performance of TEC devices as high values of these resistances can significantly diminish the effect of Peltier cooling during steady state operation. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the TEC device. High Seebeck coefficient of TE materials is desirable as it increases the figure of merit of TE devices. However, cooling capabilities of heat sink may become bottleneck to realize the benefits of very high Seebeck coefficient as the back heat flow from the hot side to cold side of TEC device diminishes the degree of cooling achieved by these ultrathin TECs.

Ultrathin Thermoelectric Devices for On-Chip Peltier Cooling

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in chip heat flux and growing concern over the emergence of on-chip “hot spots” in microprocessors, along with such high flux regions in power electronic chips and LED’s. Miniaturized thermoelectric coolers (μ-TEC’s) are a most promising cooling technique for the remediation of such hot spots. This paper presents a comprehensive review of recent advances in novel applications of superlattice, mini-contact, and silicon-based miniaturized thermoelectric coolers in reducing the severity of on-chip hot spots.

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On-chip Hot Spot Remediation with Miniaturized Thermoelectric Coolers

Sectional oblique fins are employed, in contrast to continuous fins, in order to modulate the flow in a microchannel heat sink. The breakage of continuous fin into oblique sections leads to reinitialization of boundary layers and generation of secondary flows that significantly enhance the cooling performance of the heat sink. In addition, an oblique finned microchannel heat sink has the flexibility to tailor local heat transfer performance by varying its oblique fin pitch. Clusters of oblique fins at higher density can be created in order to promote a greater degree of boundary layer redevelopment and secondary flow generation to provide more effective cooling at the high heat-flux region. Thus, the variation of oblique fin pitch can be exploited for hotspot mitigation. Experimental studies of a silicon chip with two hotspot scenarios show that the temperature hike and the temperature difference for the enhanced microchannel heat sink with variable pitch are reduced by as much as 17.1 °C and 15.4 °C, respectively. As a result, temperature distribution across the silicon chip is more uniform. In addition, the associated pressure drop penalty is much smaller than the achieved heat transfer enhancement, rendering it as an effective hotspot mitigating strategy for the single-phase microchannel heat sink.

Hotspot Mitigating With Obliquely Finned Microchannel Heat Sink—An Experimental Study

Proposed uses of solid-state thermoelectric microcoolers for hot spot remediation have included the formation of a superlattice layer on the back of the microprocessor chip, but there have been few studies on the cooling performance of such devices. This paper provides the results of 3-D, electrothermal, finite element modeling of a superlattice microcooler, focusing on the hot spot temperature and superlattice surface temperature reductions, respectively. Simulated temperature distributions and heat flow patterns in the silicon, associated with variations in microcooler geometry, chip thickness, hot spot size, hot spot heat flux, and superlattice thickness are provided. Comparison is made to hot spot cooling achieved by the Peltier effect in the silicon microprocessor chip itself. The numerical results suggest that, for a variety of operating conditions and geometries, while increasing the superlattice thickness serves to decrease the exposed superlattice surface temperature, it is ineffective in reducing the hot spot temperature below that due to the silicon Peltier effect.

Superlattice $\mu {\rm TEC}$ Hot Spot Cooling

Driven by shrinking feature sizes, microprocessor "hot-spots" - with their associated high heat flux and sharp temperature gradients - have emerged as the primary "driver" for on-chip thermal management of today's advanced IC technology. Proposed uses of solid state thermoelectric microcoolers for hot spot remediation have included the formation of a superlattice layer on the back of the microprocessor chip, but there have been few studies on the cooling performance of such devices. The present study provides the results of three-dimensional, electro-thermal, finite-element modeling of a superlattice microcooler, focusing on the achieved hot spot temperature and superlattice surface temperature reductions, respectively. Simulated temperature distributions and heat flow patterns in the silicon, associated with variations in microcooler geometry, chip thickness, hot spot size, hot spot heat flux, and superlattice thickness are provided. Comparison is made to hot spot cooling achieved by the Peltier effect in the silicon microprocessor chip itself. The numerical results suggest that, for a variety of operating conditions and geometries, while increasing the superlattice thickness serves to decrease the exposed superlattice surface temperature, it is ineffective in reducing the hot spot temperature below that due to the silicon Peltier effect.

Peng Wang

Papers

Superlattice $\mu {\rm TEC}$ Hot Spot Cooling

Impact of integrated superlattice μtec structures on hot spot remediation

On-chip hotspot thermal management with an embedded array of silicon thermoelectric microcoolers