Showing papers by "Peter A. Beerel published in 2010"

A Designer's Guide to Asynchronous VLSI

Abstract: Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications.

Timing verification of gasp asynchronous circuits: predicted delay variations observed by experiment

Abstract: This paper reports spreadsheet calculations intended to verify the timing of 6-4 GasP asynchronous Network on Chip (NoC) control circuits. The Logical Effort model used in the spreadsheet estimates the delays of each logic gate in the GasP control. The calculations show how these delays vary in response to differing environmental conditions. The important environmental variable is the physical distance from one GasP module to adjacent modules because longer wires present greater capacitance that retards the operation of their drivers. Remarkably, the calculations predict correct operation over a large range of distances provided the difference in the distances to predecessor and successor modules is limited, and predict failure if the distances differ by too much. Experimental support for this view comes from the measured behavior of a test chip called “Infinity” built by Sun Microsystems in 90 nanometer CMOS circuits fabricated at TSMC.

A Designer's Guide to Asynchronous VLSI: Single-track pipeline templates

Abstract: Introduction The single-track protocol, introduced in Chapter 2, was initially proposed by van Berkel and Blink as a communication method for bundled-data pipeline controllers. As an example, Figure 13.1 shows a single-track synchronization channel implemented with a single wire between a sender and a receiver. In this example, the sender sends a synchronization token by driving the channel wire high and the receiver detects the token and resets the channel by resetting the wire low. This is then detected by the sender, which may send a second token by raising the channel wire high again and thus repeating the entire handshaking process. An alternative form of this protocol is also possible in which the sender drives the communication wire low and the receiver drives it high. Unlike other two-phase protocols, the single-track protocol returns the communication wire to its initial state. This enables single-track templates to react to only one type of transition, avoiding the need for the complex PMOS transistor networks that are a source of area and power inefficiencies for templates that use two-phase transition signaling, i.e. a non-return-to-zero protocol. Moreover, compared with four-phase protocols the single-track protocol has fewer wire transitions, only two instead of four, to complete a handshake, leading to improved power consumption per transmitted bit. Finally, because this protocol does not use an acknowledge wire it requires fewer wires than protocols that use distinct request and acknowledge wires.