Lead-free piezoelectric K0.5Na0.5NbO3 thin films for microelectromechanical systems were fabricated via chemical solution process using metal alkoxide. Perovskite K0.5Na0.5NbO3 (KNN) single-phase thin films with good leakage current properties were successfully prepared by optimizing the KxNaxNbO3 (x0.5) composition of the precursor solution. The KNN thin films prepared from the solution with K0.55Na0.55NbO3 composition showed typical ferroelectric P–E hysteresis and field-induced strain loops. The 2Pr and 2Ec values of the K0.55Na0.55NbO3 films were 14 µC/cm2 and 140 kV/cm, respectively. From the slope of the field-induced butterfly loop, the effective d33 was found to be 46 pm/V.

https://iopscience.iop.org/article/10.1143/JJAP.46.L311/pdf

Lead-Free Piezoelectric (K,Na)NbO3 Thin Films Derived from Metal Alkoxide Precursors

The results of a comprehensive investigation into the characteristics and optimization of Inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extncts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in melallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model aecuncy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technolocies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's

Lead-free ferroelectric K0.5Na0.5NbO3 (KNN) thin films have been synthesized by the chemical solution deposition. The optimization of excess amounts of K and Na in KNN precursor solutions was found to be effective for achieving perovskite KNN single-phase thin films with improved leakage current properties. It was revealed from Raman spectroscopic analysis data that a change in scattering mode was observed for the KNN thin films fabricated under various processing conditions. This change was due to the chemical composition fluctuation of K and Na in the KNN thin films after heat treatment. The leakage current and ferroelectric properties of the perovskite KNN thin films were strongly affected by the excess amounts of K and Na as well as the heating conditions of the precursor films. Optimized KNN thin films with 10 mol % excess K and Na exhibited a ferroelectric polarization–electric field (P–E) hysteresis loop with 2Pr and 2Ec values of 14 µC/cm2 and 140 kV/cm, respectively.

https://iopscience.iop.org/article/10.1143/JJAP.46.6971/pdf

Chemical Processing and Characterization of Ferroelectric (K,Na)NbO3 Thin Films

Transmission lines are becoming of common use at mm-wave to implement on-chip functions as impedance matching, filtering and interconnects. Lack of an accurate and fast simulation method is nonetheless evident for transmission lines in scaled CMOS where metal dummies inserted for IC planarization make their physical structure extremely complicate. Although lines are not uniform due to displacement of small dummies, they are still periodic. In this paper, we describe an analytical procedure, leveraging lines periodicity and based on Floquet's theorem, in order to derive electromagnetic parameters from simulations. Conventional, slow-wave and shielded CPWs have been realized in a 65 nm CMOS technology. Thanks to the developed method, an optimum line design has been made possible. The lossy CMOS substrate, responsible for a significant performance degradation, can be effectively shielded and achieved performances are comparable with other technologies considered better suited to implement low-loss, high frequency passive components. Shielded CPW lines show attenuation as low as 0.65 dB/mm at 60 GHz, a record in scaled CMOS.

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Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations

Radio frequency (RF) power amplifiers are provided which may include high power, wideband, microwave or millimeter-wave solid state power amplifiers based on waveguide power combiner/dividers.

High frequency power combiner/divider

The increasing expansion of telecommunication applications leads to the integration of complete system-on-chip associating analog and digital processing units. Besides, the passive elements occupy an increasing silicon footprint, compromising circuit scalability and cost. Moreover, passive components’ performances are limited by the proximity of lossy Si substrate and surrounding metallization. Then, obviously, the characteristics of the substrate become crucial for monolithic radio frequency (RF) systems to reach high performances. So, looking for integrated circuit compatible processes, porous silicon (PS) seems to be a promising candidate as it can provide localized isolating regions from various silicon substrates. In this review, we first present all the possible porous silicon substrates, which can be used for RF devices. In particular, we put the emphasis on the etching conditions, leading to high thickness localized PS layers. The intrinsic electrical properties of porous silicon such as AC electrical conductivity or dielectric constant are also detailed, and the results extracted from the literature are commented. Then, we describe the performances of widespread RF devices, that is, inductors or coplanar waveguides. Finally, we describe methodologies used for predicting RF electrical responses of PS isolated devices, based on electromagnetic simulations.

Porous silicon for electrical isolation in radio frequency devices: A review

Over the last few years, thin films of PbZr x Ti 1− x O 3 (PZT) have been the focus of extensive researches for high-k capacitor applications. However, some electrical properties such as leakage current conduction and degradation mechanisms need to be better understood. From Constant Voltage Stress experiments, we identified two distinct failure mechanisms depending on the applied voltage levels. The existence of these two failure mechanisms makes it impossible to extrapolate lifetime results from high voltage to low voltage. Since the typical operating voltage for decoupling capacitors is around 3 V the reliability study has to be focused on the low voltage breakdown. A good opportunity to learn about the low voltage failure mechanisms is to investigate the characteristics of leakage current. The time evolution of leakage current is mainly controlled by the resistance degradation phenomenon. A quantitative analytical model has already been developed to account for this effect. We propose a more complete model that also includes dielectric relaxation and trapping effects. The resulting model is combined to a charge-influenced thermoionic emission model that fits fairly well the voltage and temperature dependence of leakage current. The static and dynamic parts of our model are found to be consistent, especially in terms of barrier lowering effect induced by the resistance degradation process. We believe that the low voltage breakdown is related to a trapping-induced creation of defects in the film.

Wafer level reliability and leakage current modeling of PZT capacitors

A distributed combiner/splitter having a first line formed of a first planar winding in a first conductive level and of a second planar winding in a second conductive level, and a second line formed of a third planar winding interdigited with the first winding in the first level, and of a fourth planar winding interdigited with the second winding in the second level, the windings having an increasing width from the outside to the inside.

Power combiner/splitter

Over the last few years, thin films of PbZrxTi1 − xO3 (PZT) have been the focus of extensive researches for high-k capacitor applications. However, we believe that the reliability properties and the degradation mechanisms of PZT capacitors need to be better understood. A good way to learn about failure mechanisms is to investigate the characteristics of leakage current conduction. In this paper we propose a model for current density evolution of IrO2/PZT/Pt structures as a function of time, voltage and temperature. The voltage and temperature evolution of leakage current is interpreted as an interface controlled thermoionic injection of carriers over a potential barrier at the cathode/PZT contact. The time evolution of the leakage current is mainly characterized by the resistance degradation phenomenon which results in a large increase in current density. A quantitative analytical model based on the redistribution of oxygen vacancies near the cathode interface has already been developed to account for this effect [1]. We propose a more complete model that also includes the role of oxygen vacancies on dielectric relaxation and trapping phenomena. The contributions of Pt and IrO2 electrodes on leakage current evolution are also discussed.

Leakage current conduction in IrO2/PZT/Pt structures

In this paper, we present processes to etch high thickness porous silicon layers for RF device applications. Indeed, on-chip inductors realized on bulk silicon suffer from mediocre Q-factor values mainly because of electrical losses into the substrate and capacitive coupling with the silicon appearing beyond 1 GHz. We present a detailed study of etching parameters such as the current density or the HF concentration in HF: H2O:acetic acid based electrolytes. In addition, we propose a prospective study of integrated copper inductor performances on porous silicon substrates in the range of 100 MHz to 10 GHz. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Philippe Leduc

Papers

Porous silicon for electrical isolation in radio frequency devices: A review

Wafer level reliability and leakage current modeling of PZT capacitors

Power combiner/splitter

Leakage current conduction in IrO2/PZT/Pt structures

Thick microporous silicon isolation layers for integrated RF inductors