An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An apparatus for dissociating gases includes a plasma chamber that may be formed from a metallic material and a transformer having a magnetic core surrounding a portion of the plasma chamber and having a primary winding. The apparatus also includes one or more switching semiconductor devices that are directly coupled to a voltage supply and that have an output coupled to the primary winding of the transformer. The one or more switching semiconductor devices drive current in the primary winding that induces a potential inside the chamber that forms a plasma which completes a secondary circuit of the transformer.

Toroidal low-field reactive gas source

The disclosure relates to an RF inductively coupled plasma reactor including a vacuum chamber (102) for processing a wafer (82), one or more gas sources (98, 100) for introducing into the chamber reactant gases, and an antenna (80) capable of radiating RF energy into the chamber to generate a plasma therein by inductive coupling, the antenna lying in a two-dimensionally curved surface. In another embodiment a plasma reactor includes apparatus for spaying a reactant gas at a supersonic velocity toward the portion of the chamber overlying the wafer. In a further embodiment a plasma reactor includes a planar spray showerhead for spraying a reactant gas into the portion of the chamber overlying the wafer with plural spray nozzle openings facing the wafer, and plural magnets in an interior portion of the planar spray nozzle between adjacent ones of the plural nozzle openings, the plural magnets being oriented so as to repel ions from the spray nozzle openings.

High density plasma CVD and etching reactor

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Embodiments of the invention allow a user to wirelessly transmit payment information from a mobile device to a point-of-sale terminal by the user performing only a minimum number of inputs, such as a single input. Some embodiments of the invention provide an apparatus comprising an input device configured to receive input from a user, a communication device configured to transmit wireless signals to a transaction device, a memory comprising predetermined payment information stored therein and a processor communicably coupled to the input device, the communication device and the memory and configured to: receive transaction information from the transaction device related to a transaction; receive a first input from the user; determine if the first input matches a user defined action stored in memory, and use the communication device to wirelessly transmit the predetermined payment information and authorize payment if the first input matches the user defined action stored in memory.

Single action mobile transaction device

The present invention relates to an apparatus for generating a low pressure plasma circulating in a planar direction within a process enclosure. The invention generates plasma having substantially uniform density characteristics across a planar axis. The invention achieves improved uniformity of the plasma density by delivering more radio frequency power toward the periphery of the circulating plasma than toward the center of the plasma. Increasing the periphery power to the circulating plasma compensates for increased plasma losses due to interaction with the side walls of the process containment enclosure.

Coil configurations for improved uniformity in inductively coupled plasma systems

Dynamic control and delivery of radio frequency power in plasma process systems is utilized to enhance the repeatability and uniformity of the process plasma. Power, voltage, current, phase, impedance, harmonic content and direct current bias of the radio frequency energy being delivered to the plasma chamber may be monitored at the plasma chamber and used to control or characterize the plasma load. Dynamic pro-active control of the characteristics of the radio frequency power to the plasma chamber electrode during the formation of the plasma enhances the uniformity of the plasma for more exact and controllable processing of the work pieces.

Uniform and repeatable plasma processing

A process for forming a photoresist mask over a patternable layer of an integrated circuit structure formed on a semiconductor substrate is described wherein the photoresist mask is initially formed with oversized lateral dimensions over a layer of patternable material of an integrated circuit on a semiconductor substrate. The oversized resist mask is then optionally measured in a vacuum apparatus to determine the size of the critical dimensions; then dry etched, preferably in the same vacuum apparatus, to reduce the size of the resist mask; then measured to determine the size of the critical dimensions (preferably again in the same vacuum apparatus); and then, if necessary, further dry etched to further reduce the size of the critical dimensions. The dry etching and subsequent measurement steps are repeated until the desired critical dimensions of the resist mask are reached. If the dry etching step should accidentally overetch the resist pattern, the structure can still be reworked by removing the resist mask and applying a fresh resist layer as in the prior art. After the correctly sized resist mask has been formed and determined by the cycle of dry etch and measurement steps, the underlying patternable layer can be etched through the photoresist mask, with a greatly reduced chance that the etched pattern in the underlying layer will have unsatisfactory dimensions.

Process for forming photoresist mask over integrated circuit structures with critical dimension control

Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Trench planarization techniques

A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask. The improved process of the invention comprises: forming a first hard mask layer over an upper layer of low k carbon-doped silicon oxide dielectric material previously formed over an etch stop layer formed over a lower layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first photoresist mask having a pattern of via openings therein over the first hard mask layer; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first hard mask; then removing the first photoresist mask; forming a second hard mask layer over the first hard mask; forming a second photoresist mask having a pattern of trench openings therein over the second hard mask layer; etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first and second hard masks; then removing the second photoresist mask; then using the first and second hard masks to respectively form the via openings in the lower layer of low k carbon-doped silicon oxide dielectric material and trench openings in the upper layer of low k carbon-doped silicon oxide dielectric material; whereby a pattern of via openings and a pattern of trench openings can be formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of the photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings.

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure

Philippe Schoenborn

Papers

Coil configurations for improved uniformity in inductively coupled plasma systems

Uniform and repeatable plasma processing

Process for forming photoresist mask over integrated circuit structures with critical dimension control

Trench planarization techniques

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure