A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Phase shifting circuit manufacture method and apparatus

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode. Furthermore, the barrier film prevents the electrode material from reacting with the gate dielectric material. The barrier layer is ultra thin and, at the same time, it forms a uniform cover over the entire surface of the gate dielectric.

Method of depositing barrier layer from metal gates

In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

System and method for lithography simulation

A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask. The improved process of the invention comprises: forming a first hard mask layer over an upper layer of low k carbon-doped silicon oxide dielectric material previously formed over an etch stop layer formed over a lower layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first photoresist mask having a pattern of via openings therein over the first hard mask layer; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first hard mask; then removing the first photoresist mask; forming a second hard mask layer over the first hard mask; forming a second photoresist mask having a pattern of trench openings therein over the second hard mask layer; etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first and second hard masks; then removing the second photoresist mask; then using the first and second hard masks to respectively form the via openings in the lower layer of low k carbon-doped silicon oxide dielectric material and trench openings in the upper layer of low k carbon-doped silicon oxide dielectric material; whereby a pattern of via openings and a pattern of trench openings can be formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of the photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings.

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure

The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Method and apparatus for application of proximity correction with unitary segmentation

Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer. In another method embodiment for forming a capping layer on a copper-containing conducting structure, a substrate having formed thereon electrically conducting layer comprised of a copper-containing material is provided. A layer of reactive material is then formed on the surface of the substrate. This is followed by reacting a portion of the layer of reactive material with the copper-containing material of the conducting layer to form an alloy material on the conducting layer. Unalloyed reactive material is removed from the substrate by heating the substrate to a temperature where the unalloyed reactive material desorbs from the surface of the substrate but where the alloy material remains in place on the substrate surface thereby forming a self-aligned capping layer. In another embodiment, the process is repeated iteratively until a capping layer having the desired thickness is formed.

Method for creating self-aligned alloy capping layers for copper interconnect structures

A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench

Method and apparatus for forming large scale fields suitable for use in the fabrication of integrated circuit structures having submicron dimensions. The method includes subdividing the large scale field into a plurality of subfields along the boundaries of functional components forming a very large scale integrated circuit. Stitching the subfields into the large scale field is then substantially simplified since the number and dimensions of conductive interconnects between the functional components can be more easily accommodated. The large scale field further includes a custom portion and a standard portion of functional components. Reticle formation of the standard portion involves optical correction techniques. Reticle formation of the custom portion may involve standard reticle formation techniques.

Richard Schinella

Papers

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure

Method and apparatus for application of proximity correction with unitary segmentation

Method for creating self-aligned alloy capping layers for copper interconnect structures

Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench

Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility