We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

An effective fingerprint verification system is presented. It assumes that an existing reference fingerprint image must validate the identity of a person by means of a test fingerprint image acquired online and in real-time using minutiae matching. The matching system consists of two main blocks: The first allows for the extraction of essential information from the reference image off-line, the second performs the matching itself online. The information is obtained from the reference image by filtering and careful minutiae extraction procedures. The fingerprint identification is based on triangular matching to cope with the strong deformation of fingerprint images due to static friction or finger rolling. The matching is finally validated by dynamic time warping. Results reported on the NIST Special Database 4 reference set, featuring 85 percent correct verification (15 percent false negative) and 0.05 percent false positive, demonstrate the effectiveness of the verification technique.

A fingerprint verification system based on triangular matching and dynamic time warping

In one aspect of the present invention the user can rapidly enter and search for text using a data entry system through a combination of entering one or more characters on a digitally displayed keyboard with a pointing device and using a search list to obtain a list of completion candidates. The user can activate the search list to obtain a list of completion candidates at any time while entering a partial text entry with the data entry system. When the search list is active, a list of completion candidates is displayed on a graphical user interface for the user to select from and the user can perform one of several actions. The user can deactivate the search list and return to modifying the current partial text entry and other text. The user can select one of the completion candidates in the search list and use the selected completion candidate to replace the partial text entry which the user is currently entering. When the user deactivates the interactive search list, the user can immediately continue adding to or modifying the current partial text entry being entered, and may re-invoke the search list to further search for completion candidates based on the modified partial text entry. In the second case, the selected completion candidate is used to replace the partial text entry that the user is currently entering, and the data entry system begins monitoring for a new partial text entry from the user.

Data entry for personal computing devices

This paper reviews the current state of power supply technology platforms and highlights future trends and challenges toward realizing fully monolithic power converters. This paper presents a detailed survey of relevant power converter technologies, namely power supply in package and power supply on chip (PwrSoC). The performance of different power converter solutions reported in the literature is benchmarked against existing commercial products. This paper presents a detailed review of integrated magnetics technologies, primarily microinductors, a key component in realizing a monolithic power converter. A detailed review and comparison of different microinductor structures and the magnetic materials used as inductor cores is presented. The deposition techniques for integrating the magnetic materials in the microinductor structures are discussed. This paper proposes the use of two performance metrics or figures of merit in order to compare the dc and ac performance of individual microinductor structures. Finally, the authors discuss future trends, key challenges, and potential solutions in the realization of the “holy grail” of monolithically integrated power supplies (PwrSoC).

Review of Integrated Magnetics for Power Supply on Chip (PwrSoC)

A power-efficient charge pump is proposed. The use of low-voltage transistors and of a simple two-phase clocking scheme permits the use of higher operating frequencies compared to conventional solutions, thus obtaining high current, high efficiency, and small area. Measurements show good results for frequencies around 100 MHz. Two test patterns have been fabricated, one with three stages and one with five stages, in a 1.8-V 0.18-/spl mu/m triple-well standard CMOS digital process (six metals). High-voltage capacitors have been implemented using metal to metal parasitic capacitance.

Power efficient charge pump in deep submicron standard CMOS technology

A wireless interconnection scheme based on capacitive coupling provides mono- and bi-directional transmission capabilities for 3-D system integration. Chips are implemented in 0.13 mum CMOS technology and assembled face-to-face at die-level. RX-TX circuits are specifically designed for low-power functionality and the implementation takes advantage of the two different voltage thresholds that are available for the standard transistors in the CMOS process we used. The communication circuits are coupled via electrodes with an area down to 8 times 8 mum2 and this enables the vertical propagation of clock signals at 1.7 GHz, a propagation delay of 420 ps for general purpose signals and a throughput of more than 22 Mb/s/mum2 with 0.08 pJ/b energy consumption.

3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero over head for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm2, 0.2GOPS/mW) and relatively small area occupation (18 mm2), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages.

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A dynamically adaptive DSP for heterogeneous reconfigurable platforms

A charge-pump architecture is presented with an improved power efficiency and a high voltage output compared to the known Dickson and Favrat architectures due to partial reuse of the charge stored on the capacitors. An 8-stage charge pump fabricated in a 0.13mum CMOS process has a 1.2V supply and a 100MHz clock. The measured performance indicates that the efficiency can be 25% higher than a Favrat cell. The efficiency increases with the number of stages, reaching 60% with 10 stages.

A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories

A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz. Two testpatterns have been fabricated, one with three stages and one with five stages, in a 1.8V 0.18micro;m standard CMOS digital process (6 metals) with triple well. High voltage capacitors have been implemented using metal to metal parasitic capacitance.

Pierluigi Rolandi

Papers

Power efficient charge pump in deep submicron standard CMOS technology

3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities

A dynamically adaptive DSP for heterogeneous reconfigurable platforms

A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories

Power efficient charge pump in deep submicron standard CMOS technology