We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2 $\times $ time-interleaved ADC to address the problem of comparator metastability. A 4 $\times $ time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. The decimator dissipates 13.5 mW.

Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback

This article presents a low-power audio continuous-time delta-sigma modulator (CTDSM) that employs a chopped negative-R and a tri-level finite impulse-response (FIR) DAC. The noise of the first opamp is mitigated by using a negative-R at the virtual ground of the first integrator, and the negative-R is then chopped to remove the intrinsic ${1/f}$ noise of the negative-R. The highly linear feedback DAC is realized with a 6-tap tri-level FIR-DAC whose inter-symbol interference (ISI) is kept less than −120 dB. The CTDSM fabricated in 65-nm CMOS technology occupies an active area of 0.28 mm2. It achieves 99.4-dB SNDR, 101-dB SNR, 102.8-dB dynamic range (DR), and 110.2-dB SFDR in a 24-kHz bandwidth, while consuming only $134~\mu \text{W}$ . This corresponds to a state-of-the-art figure-of-merit (FoM) of 185.3 dB.

A 134- μ W 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC

We describe the design principles and circuit details of a three-stage continuous-time pipeline (CTP) ADC that achieves 70-dB SNDR in a 100-MHz bandwidth while sampling at 800 MHz Implemented in 65-nm CMOS, the ADC is easy to drive and incorporates an inherent anti-alias filter that achieves 60-dB rejection in the first Nyquist band Each pipeline stage is realized using a second-order Rauch-filter-based residue amplifier that incorporates a 9-level resistive DAC and an RC-delay line A dummy-switching scheme relaxes DAC reference-buffer requirements The back-end ADC is a $4\times $ time-interleaved 7-bit SAR converter The Schreier and Walden FoMs of our ADC are 1654 dB and 561 fJ/level, respectively

A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth

Element mismatch in the digital-to-analog converter (DAC) of a multibit $\Delta \Sigma $ data-converter greatly degrades the modulator’s in-band performance. One approach to correct these errors is to use an offline calibration method, based on measuring the output of the modulator in response to an in-band sinusoid. The drawback of this method, however, is the necessity for a distortion-free input sine-wave excitation. We propose a technique that dispenses with the need for a distortion-free input, thereby paving the way for the generation of the input tone on-chip. Apart from being a useful tool for debugging designs, it is a potential candidate for foreground calibration. Experimental results from a multibit modulator test chip, designed in a 180nm CMOS technology, are given.

Improved Offline Calibration of DAC Mismatch Errors in Delta–Sigma Data Converters

In many data converter structures, an embedded digital-to-analog converter (DAC) is a key block, and its mismatch and dynamic errors limit the overall accuracy of the operation. Examples include multi-bit ΔΣ and incremental analog-to-digital converters (ADCs) and successive-approximation-register (SAR) ADCs. In this paper, an overview of existing methods for correcting or mitigating the effects of DAC imperfections is presented. Also, a new foreground digital correction method is described for the mitigation of static mismatch errors in the binary-weighted DAC of a multi-bit ΔΣ or incremental ADC. With minor modifications the correction processes can also be applied to the DAC of a SAR ADC, and the tuning of passive elements used in data converters.

Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial

We present design considerations for CT $\!\Delta \!\Sigma $ Ms that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT $\!\Delta \!\Sigma \text{M}$ targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB.

Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density

We present a CT$\Delta \Sigma$ M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the reference path. $1/ f$ noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB.

Prasanth Koottala

Papers

Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth