This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

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A Dynamic Zoom ADC With 109-dB DR for Audio Applications

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT $\Delta \Sigma \text{M}$ is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- $RC$ integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT $\Delta \Sigma \text{M}$ , which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 $\mu \text{W}$ from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a $1/f$ noise corner of about 3 Hz when chopped at $f_{s}/24$ .

Analysis and Design of Continuous-Time Delta–Sigma Converters Incorporating Chopping

This paper presents a low-power, high-performance continuous-time $\Sigma \Delta $ modulator for MEMS microphones front-end. The $\Sigma \Delta $ modulator 3rd-order loop filter has been implemented with a low-noise, power-optimized active-RC architecture that uses only two operational amplifiers. This solution, along with the use of a 15-level quantizer and of a feedback DAC with three-level current-steering elements, which minimizes the noise contribution for small input signals, allows achieving a DR larger than 100 dB, while consuming less than 0.5 mW, as required in always-running audio modules for portable devices. The proposed $\Sigma \Delta $ modulator, realized in $0.16\;\upmu \text{m}$ CMOS technology with an area of $0.21\;\text{mm}^{2}$ , achieves 106 dB A-weighted DR and 91.3 dB peak SNDR, consuming $390\;\upmu \text{W}$ from a 1.6 V power supply.

A 106 dB A-Weighted DR Low-Power Continuous-Time $\Sigma \Delta $ Modulator for MEMS Microphones

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional–integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 $\mu \text{W}$ with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

A 6.5- μ W 10-kHz BW 80.4-dB SNDR G m -C-Based CT ∆∑ Modulator With a Feedback-Assisted G m Linearization for Artifact-Tolerant Neural Recording

Many industrial applications require high-resolution ADCs whose low-frequency performance is important. CTDSMs are attractive due to their implicit antialiasing and resistive inputs. However, their low-frequency precision is degraded by flicker noise. The loop filter of such modulators is usually realized using active-RC techniques, and the CTDSMs' 1/f noise is mostly due to the input stage of the 1st OTA. Using large input devices to reduce 1/f noise greatly increases area occupied by the input stage, and degrades linearity due to the increased parasitic capacitance at the OTA virtual ground.

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts

We combine a first-order single-bit CT $\Delta \!\Sigma \text{M}$ employing finite impulse-response (FIR) feedback with a 1-bit second-order $\Delta \Sigma $ back end to achieve a modulator with maximum stable amplitude (MSA) that is close to full scale, and a third-order overall noise transfer function (NTF). FIR feedback is used in the input stage to reduce clock-jitter sensitivity, improve linearity, and reduce chopping artifacts. We show that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first stage that is fed into the second stage. We apply the principle to an audio continuous-time delta–sigma modulator. A prototype chip, fabricated in 180-nm CMOS to demonstrate the principle, achieves 100.9-dB SNDR in a 24-kHz bandwidth and dissipates 265 $\mu \text{W}$ . The resulting Schreier figure of merit is 180.5 dB.

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator

We present design considerations for CT $\!\Delta \!\Sigma $ Ms that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT $\!\Delta \!\Sigma \text{M}$ targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB.

Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density

We present a CT$\Delta \Sigma$ M which uses a virtual-ground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (ISI), and parasitic resistance in the reference path. $1/ f$ noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap FIR feedback DAC. Fabricated in 180nm CMOS, the prototype modulator operates at 32MS/s and achieves 103.5/107.5dB SNDR/DR in a 250kHz bandwidth while consuming 24mW. The Schreier FoM is 173.7dB.

Sujith Billa

Papers

Analysis and Design of Continuous-Time Delta–Sigma Converters Incorporating Chopping

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator

Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth