In this brief, typical locations of the interface and oxide traps generated by the hot carrier degradation (HCD) in FinFETs are studied with experiments and “atomistic” TCAD simulations under the worst case stress conditions. The typical round-Fin locations of different types of traps are analyzed by comparing the experimentally extracted results with the calibrated TCAD simulations. Then, the traps’ different impacts on HCD variations in both forward and reverse bias modes are employed to disclose the typical lateral locations of different traps. The results suggest that for both n- and p-type of FinFETs under the worst case stress conditions, the interface traps and oxide traps (type 1) are mainly distributed in the midchannel region closer to the source side on the Fin side, whereas oxide traps (type 2) are mainly distributed in the midchannel region closer to the drain side on the Fin top. Therefore, the two types of oxide traps originate in the different generation locations but may share the same atomistic structures in the same device. The results are helpful to the physical understandings of HCD in the FinFET technology.

On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

In this article, the dynamic variability induced by hot carrier degradation (HCD) in FinFETs is studied with decomposing the variation contributions of multiple types of traps. The nonlinear relationship of $\mu - \sigma ^{{2}}$ ( $\Delta {V}_{\,\text {th}}$ ) are newly observed in both n- and p-type FinFETs. A multitrap-based HCD variation model is proposed and verified in FinFETs. The impacts of HCD variations on the static random-access memory (SRAM) read/write stability are also demonstrated with the circuit simulation. The results are beneficial for the reliability-aware circuit design against HCD variability particularly for FinFET-based circuits.

Hot Carrier Degradation-Induced Dynamic Variability in FinFETs: Experiments and Modeling

We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hot-carrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration ${N} _{\text {it}}$ . These deterministic densities ${N} _{\text {it}}$ for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

We present the first physics-based approach to modeling the effect of random dopants on hot-carrier degradation (HCD) in FinFETs, which is based on a statistical analysis of HCD performed over an ensemble of 200 transistors with different random dopant configurations. As a reference, the results obtained with the deterministic version of our HCD model are used. The statistical analysis shows that degradation traces and device lifetimes have quite broad distributions and that the deterministic model tends to overestimate HCD and makes pessimistic predictions on device lifetime. Moreover, lifetime distributions evaluated for high stress voltages and for biases close to the operating regimes have different shapes which makes backward lifetime extrapolation challenging, thereby demonstrating that full physics-based HCD treatment is of crucial importance.

Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs

Using the deterministic version of our hot-carrier degradation (HCD) model, we perform a statistical analysis of the impact of random dopants (RDs) on the HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime, the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

/pdf/stochastic-modeling-of-the-impact-of-random-dopants-on-hot-1hw8puknbu.pdf

Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs

This paper reports new experimental findings about the variability of the MOSFET threshold voltage (V T ) introduced by hot carrier (HC) degradation. Previously, it was reported that the V t shift due to HC stress (ΔV t ) follows a Poissonian behavior, i.e. the standard deviation of ΔV t distribution is proportional to the square root of its mean value. Here, we show data coming from very different devices over a wide range of stress levels that deviates from the poissonian behavior under two particular conditions. First, in the initial stage of the HC stress ΔV t may exhibit a super-poissonian behavior, i.e. its standard deviation is related to the mean value yet by a power law but with an exponent larger than 0.5, that will then tend to the square root dependence as the stress continues. Second, and most notably, for very high stress levels ΔV t standard deviation tends to saturate to a maximum value, or even decrease in some cases, although HC degradation keeps increasing. A new physical model able to explain these phenomena is proposed and validated with numerical simulations. Quantitative agreement of statistical simulation with experimental data, hence predictive capability of the model, could be attained only by considering a realistic 3D geometry and the atomistic nature of both channel doping and HC induced trapped charge.

Non-poissonian behavior of hot carrier degradation induced variability in MOSFETs

A methodology is established to correlate shifts of test structure device parameters, due to device degradation or process variation, to circuit operation throughout the product lifetime. To the authors' knowledge, this work is original in that SPICE simulation is used, with degraded device models, to relate a circuit timing metric to the degradation of a discrete device used in the circuit. The correlation is validated with actual circuit measurements. In this study, the NAND Flash high-voltage switch circuit is examined in regards to the effect of degrading the p-channel MOSFET used in the circuit. Under standard operating conditions, the device degrades under high electric fields applied across the gate oxide. The method enables the accurate prediction of product lifetime using test structure measurements.

Pratap Murali

Papers

Non-poissonian behavior of hot carrier degradation induced variability in MOSFETs

Discrete Test Structure Device Degradation Analysis and Correlation to NAND Flash Circuit Operation