Silicon carbide (SiC) power devices have been investigated extensively in the past two decades, and there are many devices commercially available now. Owing to the intrinsic material advantages of SiC over silicon (Si), SiC power devices can operate at higher voltage, higher switching frequency, and higher temperature. This paper reviews the technology progress of SiC power devices and their emerging applications. The design challenges and future trends are summarized at the end of the paper.

https://ieeexplore.ieee.org/ielaam/41/8031005/7815312-aam.pdf

Review of Silicon Carbide Power Devices and Their Applications

This paper presents the design, fabrication, and comparison of different planar edge termination techniques on high-voltage 4H-SiC PiN diodes, including single- and double-junction termination extensions (JTE), floating guard rings, and a novel termination structure, the so-called "floating guard rings-assisted JTE." The influence of the anode metal edge location over different periphery regions on the breakdown voltage is also discussed, as well as the effect of a field plate and the passivation layer on the reverse characteristics. The terminations were studied by way of two-dimensional numerical device simulations and they are confirmed by fabricating and measuring 1.7-kV 4H-SiC aluminum implanted PiN diodes. It is shown that the novel termination structure provides the best results achieving the highest breakdown voltages with good production yield. The fabricated diodes also exhibited excellent forward current characteristics with a low on-state voltage drop of 3.0 V at 100 A/cm/sup 2/, thanks to the low specific contact resistivity achieved (/spl rho//sub C/=1/spl middot/10/sup -5/ /spl Omega/cm/sup 2/) after the high-temperature treatment of the anode contact. High-temperature reverse current-voltage measurements were also carried out and are presented and discussed.

Planar edge termination design and technology considerations for 1.7-kV 4H-SiC PiN diodes

Practical design of silicon carbide (SiC) Schottky diodes incorporating a field plate necessitates an understanding of how the addition of the field plate affects the performance parameters and the relationship between the diode structure and diode performance. In this paper, design rules are presented for SiC Schottky diodes that incorporate field plate edge termination. The use of an appropriate field plate edge termination can improve the reverse breakdown voltage of a SiC Schottky diode by a factor of two. Reverse breakdown voltage values can be obtained that are up to 88% of the theoretical maximums.

Design rules for field plate edge termination in SiC Schottky diodes

This paper analyzes single- and double-zone junction termination extension (JTE) structures for 4H–SiC Schottky diodes using numerical simulations. In the single-zone case, we study the effects of JTE dose, depth, length, metal/JTE overlap length, and surface or interface charge. In the double-zone case, we systematically vary the inner and outer doses over about 80 possible combinations for each of three sets of inner and outer zone widths. The total JTE width is constrained to be that necessary for optimum breakdown voltage in the single-zone case. The results are presented as contour plots of breakdown voltage and maximum surface field as a function of the two doses, with the locations of peak bulk and surface fields also indicated at each point. The resulting tolerance to variations in activated dose can then be visualized directly. The physics underlying the shapes of the contours is explained in some detail. We show that JTE behavior is significantly different for Schottky diodes compared to the better-known case of p ( i ) n junction diodes. The peak surface field is increased for Schottky diodes when the single-zone dose is reduced below its optimum value, which is opposite to the behavior of pn junctions. Moreover, double-zone JTE is not effective in reducing peak surface field for the Schottky case, unlike pn junctions, although tolerance to dose variations can be improved with two zones. The usual rule of thumb for double-zone JTE design for pn junctions is not appropriate for Schottky diodes, because of the field crowding near the sharp metal edge. We recommend an inner dose of 95–105% of the ideal single-zone and an outer dose of 70–80% of the single-zone value, with a width ratio of ∼1:1 for the inner and outer zones and a total width similar to the optimal value in a single-zone design.

Design and optimization of junction termination extension (JTE) for 4H–SiC high voltage Schottky diodes

For the first time, SiC planar p-IGBTs with 5.8 kV of blocking voltage have been fabricated and characterized. The device exhibits a differential on-resistance of ~ 570 mOmegamiddotcm2 at the gate bias of -30 V at 25degC, and decreases to ~ 118 mOmegamiddotcm2 at 200degC, ~108 mOmega middot cm 2 at 300degC, respectively. The median hole mobility in the inversion channel is 2.3 cm2/Vmiddots, and increases gradually with temperature. The effects of p-type field stopper layer and JFET region implantation to device current conduction capability were investigated. Numerical simulations have shown that to improve IGBT on-resistance, it is critical to achieve a high carrier lifetime in both drift region and JFET region, and a high value of inversion layer hole mobility

Design and Fabrications of High Voltage IGBTs on 4H-SiC

The influence of high temperature (up to 800C) annealing on the current-voltage characteristics of n-type 6H-SiC Schottky diodes is presented. Our experimental results indicate that high-temperature annealing can result in the improvement of the forw ard and reverse electrical characteristics of SiC Schottky diodes by repairing any leaky low barrier secondary diode parallel to the primary diode that may be present due to the barrier inhomogeneities at the Schottky contact interface.

The influence of high-temperature annealing on SiC Schottky diode characteristics

A new diode structure, called planar MOS-Schottky Diode (MOSSD), is proposed to reduce the reverse leakage current in SiC Schottky diode. The reverse leakage current has been reduced by one order of magnitude by using the MOSSD structure while the reverse breakdown characteristic is improved from soft breakdown to abrupt breakdown. Further, measurements on MOSSDs with thick and thin oxide MOS regions indicate that the forward current through a MOSSD with a thin oxide can be up to 90% that through a conventional Schottky diode without buried MOS structures. From high temperature measurements it is evident that the reverse characteristics of MOSSDs have less temperature dependence compared to pure Schottky diodes.

SiC planar MOS-Schottky diode: a high voltage Schottky diode with low leakage current

Current-voltage (I–V) characteristics of n- and p-type 6H−SiC Schottky diodes are compared in a temperature range of room temperature to 400°C. While the room temperature I–V characteristics of the n-type Schottky diode after turn-on is more or less linear up to ∼100 A/cm2, the I–V characteristics of the p-type Schottky diode shows a non-linear behavior even after turn-on, indicating a variation in the on-state resistance with increase in forward current. For the first time it is shown that at high current densities (>125 A/cm2) the forward voltage drop across p-type Schottky diodes is lower than that across n-type Schottky diodes on 6H−SiC. High temperature measurements indicate that while the on-state resistance of n-type Schottky diodes increases with increase in temperature, the on-state resistance of p-type Schottky diodes decreases with increase in temperature up to ∼330 K.

Comparison of current-voltage characteristics of n- and p-type 6H-SiC Schottky diodes

High current MOS-trench vertical JFETs (4H-SiC) with a blocking voltage of 600V and a low specific on-resistance of 2.86mΩ-cm 2 has been demonstrated successfully. This paper describes the static and dynamic characterization of 600V, 20A SiC MOS-enhanced JFET designed and fabricated at Rockwell Scientific. A standard double pulse test circuit with an inductive load is used for the dynamic characterization. An in-house designed and fabricated gate drive is used to drive the normally-on JFETs. The power loss and related voltage and current stresses of the SiC MOS-enhanced JFETs are measured and reported. Introduction Since the early 1990’s the silicon (Si) planar IGBT has been the power switch of choice in industrial applications. Recent development in Si IGBT technology has further enhanced the IGBT performance by increasing the device switching speed and reducing its power loss [1,2]. However, the IGBT is a bipolar device with relatively slow switching speed resulting in high switching loss. To further improve the performance of IGBT modules, advanced power diode technologies were developed to insure the full utilization of these advanced IGBT structures in power conversion applications. There have been several recent publications on advanced high voltage Si diode technology [3,4]. These technologies reduce the component voltage and current stresses, Electro-Magnetic Interference (EMI), and the overall system losses. Significant improvements can be obtained by using wide-bandgap semiconductor power switches and diodes such as silicon carbide (SiC) field effect transistors (FETs) and Schottky diodes. SiC vertical FETs are expected to out perform Si IGBTs in the 600-3000V range due to their very low on-resistance and fast switching characteristics. High voltage SiC Schottky diodes have shown promising static and dynamic characteristics for breakdown voltages up to several kV [5]. The fast switching speed and low forward voltage drop of SiC Schottky diodes can greatly reduce the total power loss and component stress as compared to Si PIN diodes. In this paper we report high current SiC MOS-enhanced Junction Field Effect Transistors (JFETs) to achieve low conduction loss and low switching loss in an inductive circuit. SiC MOS-enhanced JFETs Computer simulation results show it is possible to make a 600V SiC FET with a specific on-resistance close to 1.0 mΩ-cm 2 [6]. SiC FET devices reported in the past, with a voltage rating around 600V showed a much higher specific on-resistance than the simulated value; for examples, 18mΩ-cm 2 for 600V VJFET reported by Siemens[7] and 18mΩ-cm 2 for breakdown voltage 350-450V reported by North Carolina State University [8]. In this paper we present a new MOS-enhanced JFET to address the two major issues plaguing SiC FETs: inversion channel mobility and gate oxide reliability. Fig. 1 shows the schematic cross-section of the MOSenhanced JFET. This JFET has 4μm deep trenches with the trench bottom implanted with p-type dopants. The trenches are approximately 2μm wide and the source mesa is approximately 2μm wide. Silicon dioxide is deposited on the sidewall of the trenches, but not at their bottom. The trenches are filled with P+ polysilicon to form the gate. The P+ polysilicon contacts the implanted SiC P + region at the trench bottom that serves to shield the trench corners from high electric fields to improve gate oxide reliability. The Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1389-1392 doi:10.4028/www.scientific.net/MSF.457-460.1389 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-11/03/20,15:23:37) 2 Title of Publication (to be inserted by the publisher) forward current conducts through the channel region between the trenches through both the bulk SiC and an accumulation channel at the oxide-SiC interface instead of an inversion channel, thus ensuring low onresistance. The MOS-enhanced JFET developed at Rockwell Scientific is a normally-on FET, and requires negative gate voltage to turn-off the current. The device is capable of blocking 600V at a gate voltage of –20V, as shown in Fig. 2. The device die size is 1.4mm x 2.4mm with an active area 1mm x 2mm. The forward characteristic of a 20A MOS enhanced JFET, consisting of two dice in parallel, is shown in Fig. 3 at room temperature for 0V gate bias, 2V forward gate bias, and 4V forward gate bias. Making the gate positive relative to the source reduces the forward drop resulting in a specific on resistance of 2.86mΩ-cm 2 at a gate voltage of 4V. No gate current was observed at 4V. Fig. 1 Cross section of a MOS-enhanced JFET Fig. 2 SiC MOS-enhanced JFET with a blocking voltage of 600V at Vg=-20V. Fig. 3 The forward conduction characteristics of a 20A SiC MOS-enhanced JFET with different gate voltages. Fig.4 Schematic diagram of the double pulse test circuit Switching tests were conducted with the high current MOSenhanced JFETs turning off 20A with a SiC Schottky FWD in the standard double pulse test circuit shown in Fig. 4. The diode also consisted of two dice in parallel. Data was taken with a maximum gate voltage of 4V at a bus voltage of 300V and at both room temperature and 125°C. For all of the data the gate resistor was 8Ω. Typical room temperature turn-off waveforms are shown in Fig. 5. The gate voltage transitions from +4V to -21V. Note that the forward conduction drain voltage just prior to the turn off transient is similar to that predicted from the device’s static characteristic obtained with the curve tracer. Another observation from Fig. 5 is that the time for the drain voltage to rise (the Miller time) is much larger than the device’s -5.00E-09 0.00E+00 5.00E-09 1.00E-08 1.50E-08 2.00E-08 2.50E-08 3.00E-08 3.50E-08 0 100 200 300 400 500 600 700 Voltage (V) C u rr e n t (A ) With Vgs = -20V

Q. Zhang

Papers

Design rules for field plate edge termination in SiC Schottky diodes

The influence of high-temperature annealing on SiC Schottky diode characteristics

SiC planar MOS-Schottky diode: a high voltage Schottky diode with low leakage current

Comparison of current-voltage characteristics of n- and p-type 6H-SiC Schottky diodes

Static and Dynamic Characterization of 20A, 600V SiC MOS-Enhanced JFET