Showing papers by "Qiang Zhou published in 2019"
26 May 2019
TL;DR: Experimental results show that composite reliability optimization method can lengthen the lifetime of an entire circuit by approximately 10% compared with previous respective optimization strategy and no power noise violations exists after the composite optimization.
Abstract: Electromigration(EM) and power supply noise has been considered serious reliability issue in the power grid networks. Several performance goals in EM reliability optimization and power supply noise optimization are typically conflict with each other. In this paper, we propose a composite optimization method trading off EM and power noise optimization process. In the method, we expand a temperature-aware EM model, which takes EM transient effect into account. Experimental results show that composite reliability optimization method can lengthen the lifetime of an entire circuit by approximately 10% compared with previous respective optimization strategy and no power noise violations exists after the composite optimization.
2 citations
TL;DR: This paper proposes a feature matching method based on information flow tracking at high abstraction level that can be used to detect the Trojans and shows significantly lower time complexity compared with the existing works.
2 citations
26 May 2019
TL;DR: This paper presents a fractional-N all digital phase locked loop (ADPLL) using a retiming high linear digital phase interpolator (DPI), which is free from pre- and background-calibration, and utilizes a charge-sharing effect insensitive charge-based structure to improve the linearity.
Abstract: This paper presents a fractional-N all digital phase locked loop (ADPLL) using a retiming high linear digital phase interpolator (DPI), which is free from pre- and background-calibration. The DPI utilizes a charge-sharing effect insensitive charge-based structure to improve the linearity. Designed in a 40-nm CMOS technology, the proposed DPI achieves 9-bit resolution, 0.3ps integral nonlinearity (INL) and 0.083ps differential nonlinearity (DNL). The proposed ADPLL achieves −118 dBc/Hz in-band phase noise at 1MHz and −93.9dBc fractional spur with the 0.3ps nonlinearity of DPI.