Showing papers by "Qin Lei published in 2022"
TL;DR: In this article , the authors proposed a generalized design methodology of a robust controller to mitigate the impact of system uncertainty on controller stability and performance which includes steady-state error, disturbance rejection, high-frequency noise attenuation and speed of dynamic response.
Abstract: This paper proposes a generalized design methodology of a robust controller to mitigate the impact of system uncertainty on controller stability and performance which includes steady-state error, disturbance rejection, high-frequency noise attenuation and speed of dynamic response. The first step is to select the weighting functions that bound the transfer functions for the entire range of uncertainty. The second step is to form mathematical representation for both robust stability and robust performance. The third step is to conduct the robust H-infinity controller synthesis to generate the full-order controller, and then carry out order reduction and recheck of the design objectives. The last step is to select an optimized controller based on the multi-dimensional Pareto Front algorithm. The proposed method has been firstly applied to the current controller design of a grid-connected inverter with variable grid impedance, and secondly to the voltage controller design of an LLC resonant DC/DC converter with variable resonant capacitance. The results indicate that the selected optimal H-infinity controller has an overall more satisfactory performance in terms of stability, steady-state error, disturbance/noise rejection capability and dynamic performance, compared with conventional PI and PR controllers when there is a large variation of system parameters.
1 citations
DOI•
TL;DR: Wang et al. as discussed by the authors proposed a method combining drain-source voltage logic signal and gate signal to comprehensively detect both classic short-circuit scenarios and unique fault scenarios in series-connected SiC MOSFETs.
Abstract: Series connection of devices is an effective way to achieve higher blocking voltage. SiC MOSFETs exhibit narrow short-circuit withstand time and generally much lower short-circuit robustness than silicon IGBTs. This puts a critical concern on their utilization, further stressing the importance of reliable protection. A complete short-circuit protection should be implemented to improve the reliability. In this article, a systematic short-circuit analysis methodology is proposed. Following this methodology, all the possible fault scenarios can be derived. Besides the traditional short-circuit scenarios, some unique short-circuit faults, such as a single device short- or open- circuit, have been found in series-connected SiC MOSFETs. These unique faults may not cause overcurrent, which means the traditional overcurrent-based protection is not applicable. This article proposes a method combining drain-source voltage logic signal and gate signal to comprehensively detect both classic short-circuit scenarios and unique fault scenarios. Another different point in series-connected devices is that the soft turn-off should be synchronized for each serial device to prevent excessive voltage unbalancing. The proposed short-circuit protection scheme is evaluated under each short-circuit scenario. The experimental results demonstrate that the proposed protection scheme can successfully protect the serial devices from further destruction within 500 ns for all short-circuit scenarios.
1 citations
TL;DR: In this paper , the authors proposed a novel multilevel topology called modular isolated-isolated-multilevel-converter (MIMC) which achieves almost zero low frequency capacitor voltage fluctuation.
Abstract: This paper proposes a novel multilevel topology “Modular-Isolated-Multilevel-Converter” which achieves almost zero low frequency capacitor voltage fluctuation. It inherits the structure of MMC but replaces the half bridge module by the newly proposed Isolated Half-Bridge (IHB). The fundamental and 2nd order harmonic frequency current originally in the MMC module capacitor have been eliminated through connecting the secondary sides of the IHB at the same level of the three phases together. The elimination is due to that the 1st and 2nd order components in the arm current are 120° phase shifted in three phases. Therefore, the module capacitance is reduced by more than 10 times since it only carries switching frequency ripple. Moreover, the arm inductance can also be significantly reduced since the 2nd order harmonic current disappears. The topology is specifically suitable for variable frequency drive application, because its capacitance and inductance are not affected by the output frequency. The challenges of zero frequency start-up when MMC is adopted for VSD can be addressed here. In the paper, the operation principle of the proposed MIMC is fully analyzed and the mathematical model is built. Moreover, a methodology of capacitor sizing and arm inductor design for general MMC topology is proposed. The detailed design considerations for MIMC are also discussed and presented. The plant modeling and control strategy have been proposed for MIMC. A 55-kW simulation is carried out to verify the theoretical analysis. And a 6-kW downscaled hardware prototype is also developed to demonstrate the benefits of the new topology over the traditional MMC.