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Optical Networks A Practical Perspective

A detailed analysis of fundamental tradeoffs between ring radius and coupling gap size is presented to draw realistic borders of the possible design space for microring resonators (MRRs). The coupling coefficient for the ring-waveguide structure is estimated based on an integration of the nonuniform gap between the ring and the waveguide. Combined with the supermode analysis of two coupled waveguides, this approach is further expanded into a closed-form equation that describes the coupling strength. This equation permits to evaluate how the distance separating a waveguide from a ring resonator, and the ring radius, affect coupling. The effect of ring radius on the bending loss of the ring is furthermore modeled based on the measurements for silicon MRRs with different radii. These compact models for coupling and loss are subsequently used to derive the main optical properties of MRRs, such as 3-dB optical bandwidth, extinction ratio of resonance, and insertion loss, hence identifying the design space. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5–10 $\mu$ m in radius and gap sizes ranging from 120 to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects.

Design Space Exploration of Microring Resonators in Silicon Photonic Interconnects: Impact of the Ring Curvature

Optical on-chip data transmission enabled by silicon photonics (SiP) is widely considered a key technology to overcome the bandwidth and energy limitations of electrical interconnects. The possibility of integrating optical links into the on-chip communication fabric has opened up a fascinating new research field—Optical Networks-on-Chip (ONoCs)—which has been gaining large interest by the community. SiP devices and materials, however, are still evolving, and dealing with optical data transmission on chip makes designers and researchers face a whole new set of obstacles and challenges. Designing efficient ONoCs is a challenging task and requires a detailed knowledge from on-chip traffic demands and patterns down to the physical layout and implications of integrating both electronic and photonic devices. In this paper, we provide an exhaustive review of recently proposed ONoC architectures, discuss their strengths and weaknesses, and outline active research areas. Moreover, we discuss recent research efforts in key enabling technologies, such as on-chip and adaptive laser sources, automatic synthesis tools, and ring heating techniques, which are essential to enable a widespread commercial adoption of ONoCs in the future.

A Survey on Optical Network-on-Chip Architectures

In sharing economy, people offer idle social resources to others in a sharing manner. Through community-based online platforms, the people offering services can earn commission while others can enjoy a better life via renting social resources. Consequently, the value-in-use of services is expectedly strengthened within the unit time, although the total amount of social resources remains constant. Influenced by sharing economy, some famous companies have developed intelligent systems to analyze the most appropriate coincidence between citizens’ idle supply and renting demand from numerous data sets. However, the big data analysis of the optimal service-demand matching usually runs on the traditional multiprocessors equipped in intelligent systems, so-called “system-on-chip.” In this paper, we design a novel computer architecture—the accelerator based on optical network-on-chip (ONoC)—to further speed up the matching between citizens’ offer and demand in sharing economy. Our ONoC-based accelerator is able to quickly calculate the optimal service-demand matching by processing computation tasks on parallel cores, i.e., task-core mapping. In addition, to improve the accelerator reliability, the assorted task-core mapping algorithm is also designed. The extensive simulation results based on real trace file demonstrate the effectiveness of our system and algorithm. Note to Practitioners —Sharing economy is of great importance for realizing green consumption and sustainable development in our human society. Sharing economy enterprise calls for intelligent system design for service-demand matching in the current big data era. In this paper, we design the accelerator based on ONoC to further speed up the matching between citizens’ offer and demand in sharing economy. By processing computation tasks on parallel cores using our algorithm, the task-core mapping can be performed with high speed and reliability. The simulation results—based on the trace file of Amazon Mechanical Turk—can well guide the practitioners to design a more clever and reliable product by quickly calculating the optimal service-demand matching.

Quick Answer for Big Data in Sharing Economy: Innovative Computer Architecture Design Facilitating Optimal Service-Demand Matching

Silicon photonic interconnect (SPI) is an attractive alternative for the power-hungry and low-bandwidth metallic interconnect in multiprocessor systems-on-chip (MPSoCs). When employing SPIs for wavelength-division multiplexing (WDM)-based applications, it is essential to precisely align the central wavelengths of different photonic devices (e.g., photonic switches) to achieve a reliable communication. However, SPIs are sensitive to fabrication nonuniformity (a.k.a. fabrication process variation), which results in wavelength mismatches between devices, and hence performance degradation in SPIs. This work presents a computationally efficient and accurate bottom-up approach to study the impact of fabrication process variations on passive silicon photonic devices and interconnects. We first model the impact of process variations at the component level (i.e., strip waveguides), then at the device level (i.e., add-drop filters and photonic switches), and finally at the system level (i.e., passive WDM-based SPIs). Numerical simulations are performed not only to evaluate the accuracy of our method, but also to demonstrate its high-computational efficiency. Furthermore, our study includes the design, fabrication, and analysis of several identical microresonators to demonstrate process variations in silicon photonics fabrication. The efficiency of our proposed method enables its application to large-scale passive SPIs in MPSoCs, where employing time-consuming numerical simulations is not feasible.

Chip-Scale Silicon Photonic Interconnects: A Formal Study on Fabrication Non-Uniformity

Optical networks-on-chip (ONoCs) using wavelength-division multiplexing (WDM) technology have progressively attracted more and more attention for their use in tackling the high-power consumption and low bandwidth issues in growing metallic interconnection networks in multiprocessor systems-on-chip. However, the basic optical devices employed to construct WDM-based ONoCs are imperfect and suffer from inevitable power loss and crosstalk noise. Furthermore, when employing WDM, optical signals of various wavelengths can interfere with each other through different optical switching elements within the network, creating crosstalk noise. As a result, the crosstalk noise in large-scale WDM-based ONoCs accumulates and causes severe performance degradation, restricts the network scalability, and considerably attenuates the signal-to-noise ratio (SNR). In this paper, we systematically study and compare the worst case as well as the average crosstalk noise and SNR in three well-known optical interconnect architectures, mesh-based, folded-torus-based, and fat-tree-based ONoCs using WDM. The analytical models for the worst case and the average crosstalk noise and SNR in the different architectures are presented. Furthermore, the proposed analytical models are integrated into a newly developed crosstalk noise and loss analysis platform (CLAP) to analyze the crosstalk noise and SNR in WDM-based ONoCs of any network size using an arbitrary optical router. Utilizing CLAP, we compare the worst case as well as the average crosstalk noise and SNR in different WDM-based ONoC architectures. Furthermore, we indicate how the SNR changes in respect to variations in the number of optical wavelengths in use, the free-spectral range, and the microresonators $\boldsymbol {Q}$ factor. The analyses’ results demonstrate that the crosstalk noise is of critical concern to WDM-based ONoCs: in the worst case, the crosstalk noise power exceeds the signal power in all three WDM-based ONoC architectures, even when the number of processor cores is small, e.g., 64.

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison

Chip I/O pins are an increasingly limited resource and significantly affect the performance, power and cost of multicore processors. Optical interconnects promise low power and high bandwidth, and are potential alternatives to electrical interconnects. This work systematically developed a set of analytical models for electrical and optical interconnects to study their structures, receiver sensitivities, crosstalk noises, and attenuations. We verified the models by published implementation results. The analytical models quantitatively identified the advantages of optical interconnects in terms of bandwidth, energy consumption, and transmission distance. We showed that optical interconnects can significantly reduce chip pin counts. For example, compared to electrical interconnects, optical interconnects can save at least 92% signal pins when connecting chips more than 25 cm (10 inches) apart.

Qinfen Hao

Papers

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison

Alleviate chip I/O pin constraints for multicore processors through optical interconnects