Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

/pdf/current-status-and-opportunities-of-organic-thin-film-3mp8edo8oe.pdf

Current Status and Opportunities of Organic Thin-Film Transistor Technologies

Energy harvesting is gaining more and more attentions due to its characteristics of ultra-long operation time without maintenance. However, frequent unpredictable power failures from energy harvesters bring performance and reliability challenges to traditional processors. Nonvolatile processors are promising to solve such a problem due to their advantage of zero leakage and efficient backup and restore operations. To optimize the nonvolatile processor design, this paper proposes new metrics of nonvolatile processors to consider energy harvesting factors for the first time. Furthermore, we explore the nonvolatile processor design from circuit to system level. A prototype of energy harvesting nonvolatile processor is set up and experimental results show that the proposed performance metric meets the measured results by less than 6.27% average errors. Finally, the energy consumption of nonvolatile processor is analyzed under different benchmarks.

Ambient energy harvesting nonvolatile processors: from circuit to system

Thin-film electronics has hugely benefitted from low-cost processes, large-area processability, and multifunctionality. This has not only stimulated innovation in display and sensor technology but has also demonstrated great potential for the integration of components for human–machine interfaces. For electronics to be deployed as sensor interfaces and signal processing, the quest for low power is compelling due to the inherently limited battery lifetime. This review will present the state of the art in thin-film electronics and demonstrate examples of low-cost printable transistors and biosensors that are flexible/stretchable for wearable and other applications. Ultralow-power design for thin-film transistors will be discussed from the standpoint of reducing both operating voltage and operating current, taking into account the challenges in meeting frequency requirements. Compact models for circuit design will be reviewed along with new insights into ultralow-power transistors and high-gain amplifier circuits. Finally, a concept for an integrated system comprising sensors and interfacing circuits will be demonstrated, which has the potential to enable batteryless operation.

/pdf/flexible-ultralow-power-sensor-interfaces-for-e-skin-q5rr0j7u07.pdf

Flexible Ultralow-Power Sensor Interfaces for E-Skin

Nonvolatile processor (NVP) attracts more and more attentions for its immunity to power loss in energy harvesting scenarios The overall performance of an NVP is determined by its sleep and wake-up speeds, which refer to how fast the NVP can turn itself off and on when a sudden power failure occurs To the best of our knowledge, this paper is the first work to improve the system-level sleep/wake-up speed of an energy harvesting NVP A hybrid CMOS/ferroelectric nonvolatile flip-flop (nvFF) and a high-speed voltage detector are designed and integrated in the proposed NVP to jointly minimize its sleep and wake-up time Measurement results demonstrate $46~\mu \text {s}$ wake-up time and $14~\mu \text {s}$ sleep time, which is up to 18 and 24 times speedup over existing works This approach not only improves the robustness of the NVP to power fluctuations but also brings significant advantages for better utilization of harvested energy

A Ferroelectric Nonvolatile Processor with 46 $\mu $ s System-Level Wake-up Time and 14 $\mu $ s Sleep Time for Energy Harvesting Applications

Energy harvesting is one of the most promising battery alternatives to power future generation embedded systems in Internet of Things (IoT). However, energy harvesting powered embedded systems suffer from frequent execution interruption due to unstable energy supply. To bridge intermittent program execution across different power cycles, non-volatile processor (NVP) was proposed to checkpoint register contents during power failure. Together with register contents, the cache contents also need to be preserved during power failure. While pure non-volatile memory (NVM) based cache is an intuitive option, it suffers from inferior performance due to high write latency and energy overhead. In this paper, we will propose replacement and checkpoint policies for SRAM and NVM based hybrid cache in NVPs whose execution is interrupted frequently. Checkpointing aware cache replacement polices and smart checkpointing polices are proposed to achieve satisfactory performance and efficient checkpointing upon a power failure and fast resumption when power returns. The experimental results show that the proposed architectures and polices outperform existing cache architectures for NVPs.

https://dl.acm.org/doi/pdf/10.1145/2968456.2968477

Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems

Flexible capacitive pressure sensing system (FCPSS) is promising in the area of healthcare, robotics, and Internet of Things (IoT). As the size of the sensing array increases, designing energy-efficient FCPSS is getting challenging. This work provides a comprehensive solution for low-power FCPSS design, where major contributions are as follows. 1) Crosstalk-induced measurement error in a crossbar structure FCPSS is first studied and an accurate and low-power linear iterative algorithm is proposed for on-chip sensing array calibration (SAC). 2) Binary Neural Network (BNN)-based spatial-temporal adaptive sensing scheme for FCPSS is first proposed to utilize the sparsity of sampling and to further improve energy efficiency. Combined with the clock-gating-friendly low-power sensor interface, the system consumes 31.39 μJ energy and gains 95.04% capacitor measurement accuracy for each sensing operation on a 10×10 array, achieving 116× energy reduction compared with the state-of-the-art technology.

An Energy-Efficient Flexible Capacitive Pressure Sensing System

Event cameras are event driven bio-inspired sensors owning to the advantages: high temporal resolution, high dynamic range, low power, and high imaging speed. Artiﬁcial neural networks (ANNs) cannot directly process their output spike signal. Spiking neural networks are neuromorphic computing methods with high temporal resolution and event-driven which ﬁts well with event cameras. However, the deep SNNs consume large storage space and neuronal computing resources, which limits its deployment in Mobile Edge Computing. Based on feature dimension mapping, this paper proposes a lightweight SNN for embedded devices to reduce storage requirements, improve eﬃciency and enhance network performance. Firstly, by analyzing the relationship between the parameter number and the ﬁtting function of the network, the parameter bottleneck of SNN is clear. Sub-sequently, a general lightweight feature extraction structure, SpikeFire, is proposed based on a low-dimensional feature extraction − fusion strategy, which greatly reduces network parameters on the premise that the basic properties of the receptive ﬁeld and feature dimension are the same as spiking convolution. In addition, the module simulates the complex connection of the brain and adopts the skip connection, which not only increases the extraction of multi-scale information but also contributes to the optimization of the deep network. Finally, the lightweight network is deployed in embedded hardware to build an event-driven imaging recognition system. Experiments show that our method can reduce the number of parameters and improve the running speed without weakening the performance in public, self-built real scenes, and extreme imaging scenes datasets.

Towards event camera signal recognition with lightweight spiking

Despite the large noise margin merit of pseudo- CMOS logic, its analytical model is absent. In this paper, we derive the static noise margin model for pseudo-CMOS (pseudo- D) logic circuits. Finally, we analyze the impact of design parameters on noise margin. Simulations show the modeling error is about 3%.

Qinghang Zhao

Papers

An Energy-Efficient Flexible Capacitive Pressure Sensing System

Towards event camera signal recognition with lightweight spiking

Noise margin analysis for Pseudo-CMOS circuits