Yongpan Liu

TL;DR: This work proposes a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory, and distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving.

TL;DR: The simulation platform in this paper is calibrated using measured results from a fabricated nonvolatile processor and used to explore the design space for a nonVolatile processor with different architectures, different input power sources, and policies for maximizing forward progress.

TL;DR: GraphH, a PIM architecture for graph processing on the hybrid memory cube array, is proposed to tackle all four problems mentioned above, including random access pattern causing local bandwidth degradation, poor locality leading to unpredictable global data access, heavy conflicts on updating the same vertex, and unbalanced workloads across processing units.

TL;DR: New metrics of nonvolatile processors to consider energy harvesting factors for the first time are proposed and the nonvolatility processor design from circuit to system level is explored.

TL;DR: A 65nm fully-CMOS-logic-compatible ReRAM-based NVP achieving time/space-adaptive data retention and adaptive retention and SWT strategy relieve the ReRAM write endurance challenge, making it sufficient for most applications.