Showing papers by "Qingjiang Li published in 2018"
TL;DR: Various synaptic functions, including short-term Plasticity, long-term plasticity, pair-pulse facilitation, and spike timing-dependent Plasticity have been successfully eliminated in Ag/GeSe/TiN devices.
Abstract: The electronic synapse, which can vividly emulate short-term and long-term plasticity, as well as voltage sensitivity, in the bio-synapse, is the vital device foundation for brain-inspired neuromorphic computing. In this letter, we propose a Ag/GeSe/TiN memristor as an electronic synapse for brain-inspired neuromorphic applications. Due to the electromigration and diffusion of Ag cation, the volatile and non-volatile switching behaviours are coexistent in this device. Various synaptic functions, including short-term plasticity, long-term plasticity, pair-pulse facilitation, and spike timing-dependent plasticity, have been successfully eliminated in Ag/GeSe/TiN devices. Furthermore, all the synaptic functions are induced by the spiking stimuli with amplitudes of several hundred millivolts. All the results demonstrate that the Ag/GeSe/TiN device has great potential for brain-inspired computing systems in the future.
54 citations
TL;DR: In this paper, a Ti/AlO x/TaO x /Pt memristor was proposed as an analog synapse for memristive neural network applications, which shows high uniformity, excellent analog switching behaviors (up to 200 resistance states under triangle pulses) and excellent long-term retention of each state.
Abstract: Electronic synapse with precise analog weight tuning ability and long-term retention is the vital device foundation of memristor-based neuromorphic computing systems In this letter, we propose a Ti/AlO x /TaO x /Pt memristor as an analog synapse for memristive neural network applications The device shows high uniformity, excellent analog switching behaviors (up to 200 resistance states under triangle pulses) and excellent long-term retention of each state (up to 30 000 s) Furthermore, the precise modulation of the device resistance state (with 17% tolerance) can also be achieved by a finer writing program within 50 cycles
36 citations
TL;DR: In this paper, annealing process is implemented to improve the performance of programmable metallization cell selectors, revealing the potential as selector for cross-point memristor array.
Abstract: Programmable metallization cell is one of important threshold switching selectors. We first performed a study on the selector based on amorphous chalcogenide material (Si0.4Te0.6) because of the rigid structure applied in ovonic threshold switch. In the meantime, annealing process is implemented to improve the performance. Results show that devices without annealing process demonstrate a minor threshold switching characteristic, revealing the potential as selector for cross-point memristor array. After implementing annealing process, threshold voltage ( $V _{\mathrm{ th}}$ ), selectivity and endurance of selectors improve. Meanwhile, requirements of high current and a low holding voltage ( $V _{\mathrm{ h}}$ ) for an ideal selector are fulfilled. Using the Ag filament formed during motion of Ag ions, a steep-slope (1.7 mV/dec) for threshold switching with high selectivity (~104) could be achieved. Owing to the faster diffusivity of Ag atoms in solid-electrolytes, the resulting Ag filament easily dissolved under low current regime. It is deduced that performance improvement is due to the defect reduction within annealing process. Finally, time characteristics of selector devices are tested to verify fast switching and recovery speed for practical applicability.
25 citations
08 Jul 2018
TL;DR: A low-power neural network architecture is proposed that utilizes the memristor crossbar to store weights to execute convolution operation in parallel, and is presented as the spiking convolutional neural networks.
Abstract: With the rapid development of VLSI industry, the research of intelligent applications moves towards IoT edge computing. While the power consumption and area cost of deep neural networks usually exceed the hardware limitation of edge devices. In this paper, we propose a low-power neural network architecture to address such problem. We simplify the current popular convolutional neural networks structure, and utilize the memristor crossbar to store weights to execute convolution operation in parallel, and we present the spiking convolutional neural networks. At the same time, we proposed a performance metrics V to help provide design guidelines for choosing the parameters of the network.
12 citations
01 Jan 2018
TL;DR: A single layer SNN architecture based on the characteristics of spiking timing dependent plasticity (STDP) in accordance with the actual test of the device data has been proposed.
Abstract: In order to gain a better understanding of the brain and explore biologically-inspired computation, significant attention is being paid to research into the spike-based neural computation. Spiking neural network (SNN), which is inspired by the understanding of observed biological structure, has been increasingly applied to pattern recognition task. In this work, a single layer SNN architecture based on the characteristics of spiking timing dependent plasticity (STDP) in accordance with the actual test of the device data has been proposed. The device data is derived from the Ag/GeSe/TiN fabricated memristor. The network has been tested on the MNIST dataset, and the classification accuracy attains 90.2%. Furthermore, the impact of device instability on the SNN performance has been discussed, which can propose guidelines for fabricating memristors used for SNN architecture based on STDP characteristics.
3 citations
01 Nov 2018
TL;DR: A Link-Sharing method is proposed which propagates congestion information on the normal data links during their idle cycles to improve the NoC saturation point and enables each router to have a more detailed and timely updated network status overview than counterpart congestion aware routing algorithms.
Abstract: Congestion aware routing plays an important role in balancing the Networks-on-Chip (NoC) traffic load to diminish the communication cost. Theoretically, the more detailed network congestion information is collected, the better routing decision can be made. However, the congestion information propagation methods employed by state of the art designs usually have drawbacks like long update interval, nonnegligible link wiring overhead, or can only propagate abbreviated congestion information. Noticing that NoC link utilization rate is typically low, we propose a Link-Sharing method which propagates congestion information on the normal data links during their idle cycles. Be benefited from the wide link bandwidth, Link-Sharing enables each router to have a more detailed and timely updated network status overview than counterpart congestion aware routing algorithms, and thus can make more sophisticated routing decision to avoid the congested area. When compared with the counterpart methods, Link-Sharing is able to improve the NoC saturation point by up to 20.8 % with negligible area and power overhead.
1 citations
Patent•
04 Sep 2018
TL;DR: In this paper, a mismatch adaptive calibration method for a sample hold circuit of a dual-channel TIADC was proposed, where a mismatch parameter is estimated in a process of reconstructing the modulo-2 quasi-stationary property of an output signal, a mismatch error is reconstructed by adopting a variable multiplier and a differentiator, and the calibration performance is enhanced by means of Richardson iteration.
Abstract: The invention relates to a mismatch adaptive calibration method for a sample hold circuit of a dual-channel TIADC. A mismatch parameter is estimated in a process of reconstructing the modulo-2 quasi-stationary property of an output signal, a mismatch error is reconstructed by adopting a variable multiplier and a differentiator, and the calibration performance is enhanced by means of Richardson iteration. According to the method, the spectrum utilization efficiency is improved, and the complexity of filter design is not remarkably increased.
Patent•
06 Apr 2018
TL;DR: In this paper, the authors proposed an ultra-fast response RRAM electrical characteristic measurement current-limiting circuit, which includes a zero-crossing detection module, a current measurement module, and a current limiting judgment module, where the current judgment module mainly judges whether IRT reaches a set current limit value or not.
Abstract: The present invention relates to an ultra-fast response RRAM electrical characteristic measurement current-limiting circuit. According to the current-limiting circuit, the overall response time of thecurrent-limiting circuit is reduced to a level of 100 ns by using the low-latency characteristic of a high-speed circuit element. The current-limiting circuit specifically includes a zero-crossing detection module, a current measurement module and a current limiting judgment module, wherein the current limiting judgment module mainly judges whether IRT reaches a set current limit value or not. With the ultra-fast response RRAM electrical characteristic measurement current-limiting circuit of the invention adopted, the problems of low current limiting speed and low precision in an RRAM electrical characteristic measurement process can be solved.