In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

Active Gate Driver for Crosstalk Suppression of SiC Devices in a Phase-Leg Configuration

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

Methodology for Wide Band-Gap Device Dynamic Characterization

In this paper, a review of switching loss mechanisms for synchronous buck voltage regulators (VRs) is presented. Following the review, a new simple and accurate analytical switching loss model is proposed for synchronous buck VRs. The model includes the impact of common source inductance and switch parasitic inductances on switching loss. The proposed model uses simple equations to calculate the rise and fall times and piecewise linear approximations of the high-side MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss in a synchronous buck VR. A simulation program with integrated circuit emphasis (Spice) simulations are used to demonstrate the accuracy of the voltage source driver model operating in a 1-MHz synchronous buck VR at 12-V input, 1.3-V output. Switching loss was estimated with the proposed model and compared to Spice measurements. Experimental results are presented to demonstrate the accuracy of the proposed model.

A Practical Switching Loss Model for Buck Voltage Regulators

An RF transmitter (30) includes an RF power amplifier (32) for which the power input bias voltage (40) and signal input bias voltage (80) are controlled within feedback loops. A peak detector (44) generates a lowered-spectrum, peak-tracking signal (34) that follows the largest amplitude peaks of a wide bandwidth communication signal (16) but exhibits a lower bandwidth. This signal (34) is scaled in response to the operation of a drain bias tracking loop (146) then used to control a switching power supply (36) that generates the power input bias voltage. The tracking loop (146) is responsive to out-of-band power detected in a portion of the amplified RF communication signal (16'). A ratio of out-of-band power (128) to in-band power (126) is manipulated in the tracking loop (146) so that the power input bias voltage is modulated in a way that holds the out-of-band power at a desired predetermined level.

Rf transmitter with variably biased rf power amplifer and method therefor

Advanced power semiconductor devices, especially wide band-gap devices, have inherent capability for fast switching. However, due to the limitation of gate driver capability and the interaction between two devices in a phase-leg during switching transient (cross talk), the switching speed is slower than expected in practical use. This paper focuses on identifying the key limiting factors for switching speed. The results provide the basis for improving gate drivers, eliminating interference, and boosting switching speed. Based on the EPC2001 Gallium Nitride transistor, both simulation and experimental results verify that the limiting factors in the gate loop include the pull-up (-down) resistance of gate driver, rise (fall) time and amplitude of gate driver output voltage; among these the rise (fall) time plays the primary role. Another important limiting factor of device switching speed is the spurious gate voltage induced by cross talk between two switches in a phase-leg. This induced gate voltage is not only determined by the switch speed, but also depends on the gate loop impedance, junction capacitance, and operating conditions of the complementary device.

Analysis of the switching speed limitation of wide band-gap devices in a phase-leg configuration

Good understanding of power loss in a high frequency synchronous buck converter is important for design optimization of both discrete and system level. Most of the power losses are relatively easy to quantify. The exception is the power loss associated with Cdv/dt induced turn on of the low-side metal oxide semiconductor field effect transistor (synchronous rectifier). This paper characterizes the Cdv/dt induced power loss in two ways. First, detailed device characterization, in-circuit testing, and modeling are used for a comparative loss calculation. This method offers detailed loss breakdown but requires specialized test equipment and is rather complicated and time consuming. A simple method is then introduced to accurately quantify the Cdv/dt loss. With this method, the Cdv/dt induced power loss on synchronous buck converters at different operation conditions can be readily assessed. The impacts of Cdv/dt induced loss on different applications are addressed. Finally, the design tradeoffs at both discrete and system levels are discussed.

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Characterization of $Cdv/dt$ Induced Power Loss in Synchronous Buck DC–DC Converters

Good understanding of power loss in a high frequency synchronous buck converter is important for design optimization of both power MOSFET and circuit itself. Most of the MOSFET power losses are relatively easy to quantify. The exception is the power loss associated with Cdv/dt induced turn on of the low-side MOSFET (synchronous rectifier). This paper characterizes the Cdv/dt induced power loss in two ways. First, detailed device characterization, in-circuit testing, and modeling are used for a comparative loss calculation. This method requires specialized test equipment and is rather complicated and time consuming. A simple method is then introduced to very accurately quantify the Cdv/dt loss. With this method, the Cdv/dt induced power loss on synchronous buck converters at different operation conditions can be readily assessed. The impacts of Cdv/dt induced turn on different applications are addressed.

/pdf/characterization-of-cdv-dt-induced-power-loss-in-synchronous-13dnsry2gh.pdf

Qun Zhao

Papers

Characterization of $Cdv/dt$ Induced Power Loss in Synchronous Buck DC–DC Converters

Characterization of Cdv/dt induced power loss in synchronous buck DC-DC converters