High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.

Time interleaved converter arrays

A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.

https://www.ee.columbia.edu/~kinget/EE6312_S04/project/refs/lewis_pipelined_ad_jssc_dec_1987.pdf

A pipelined 5-Msample/s 9-bit analog-to-digital converter

The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation. >

Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity (DNL) and 2 b in integral nonlinearity (INL) in a flash analog-to-digital converter (ADC). Fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process, the circuit measures 1.4 mm/spl times/1.4 mm including a bandgap and a sample-and-hold (SH), while the ADC itself occupies 1-mm/sup 2/. At a conversion rate of 50-MS/s the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB S/(N+D) with a 12-MHz 90% full-scale input.

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm/sup 2/

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.

An 8-MHz CMOS subranging 8-bit A/D converter

A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.

A high-speed 7 bit A/D converter

The sigma-delta modulation principle is used in a five-digit plus-sign A/D converter. A simple auto-zero circuit is added to eliminate input-offset problems. Two input voltage ranges can be chosen in a cold-switched range-setting mode. The analog subsystem is implemented into two integrated circuits and contains nearly all necessary elements. Only a timer and up/down counter circuit are required to obtain the digital output signal.

R.E.J. van Der Grift

Papers

A high-speed 7 bit A/D converter

A five-digit analog-digital converter