A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

A physically based mobility model for numerical simulation of nonplanar devices

Although it has been qualitatively demonstrated that surface roughness can reduce the thermal conductivity of crystalline Si nanowires (SiNWs), the underlying reasons remain unknown and warrant quantitative studies and analysis. In this work, vapor–liquid–solid (VLS) grown SiNWs were controllably roughened and then thoroughly characterized with transmission electron microscopy to obtain detailed surface profiles. Once the roughness information (root-mean-square, σ, correlation length, L, and power spectra) was extracted from the surface profile of a specific SiNW, the thermal conductivity of the same SiNW was measured. The thermal conductivity correlated well with the power spectra of surface roughness, which varies as a power law in the 1–100 nm length scale range. These results suggest a new realm of phonon scattering from rough interfaces, which restricts phonon transport below the Casimir limit. Insights gained from this study can help develop a more concrete theoretical understanding of phonon–surfac...

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Quantifying surface roughness effects on phonon transport in silicon nanowires.

A comprehensive study on the inversion layer mobility improvement of n-channel MOSFETs with nanometer-range ultra-thin (reoxidized) nitrided oxides is presented. The performance improvement is described from both the device physics modeling and device/circuit design points of view by using the various kinds of current drivability and mobility data over wide ranges of gate drive and E/sub eff/. The nitridation- and reoxidation-condition dependencies of the mobility values are extensively reported. A mechanism for improvement is discussed in conjunction with the observed results of Auger electron spectroscopy, capacitance-voltage measurements, hole mobility measurements of p-channel MOSFETs, and transmission electron microscopy. The (reoxidized) nitrided oxides were fabricated fully by rapid thermal processing instead of conventional quartz-tube furnace annealing, whose major drawback is a considerable redistribution of dopant impurities. >

Inversion layer mobility under high normal field in nitrided-oxide MOSFETs

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale. The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that Pb concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen. Finally, the roles of contamination, particles, metals, hydrocarbons etc. are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above.

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Oxidation of silicon: the VLSI gate dielectric

An overview of the growth and characterization of epitaxial insulators on semiconductors is presented. The potential applications include semiconductor-on-insulator structures, three-dimensional and/or high-density integrated circuits, optoelectronic applications such as integrated waveguides and improved gate insulators. The growth and physical characterization of epitaxial fluorides on semiconductors are discussed. Consideration is also given to the epitaxial overgrowth of epitaxial metal layers with CaF2 as well as to the formation of a novel superlattice of Ca particles in epitaxial CaF2.

Growth and characterization of single crystal insulators on silicon

Scattering of inversion layer electrons at the oxide semiconductor interface is a major source of mobility degradation in MOSFETs. We have studied, on the same sample, high resolution TEM cross sections of the Si–SiO2 interface and detailed temperature dependent electronic and magnetic transport measurements. The expeirmental mobility data are compared to a model containing terms for surface roughness and impurity scattering including carrier screening. The statistical properties of the interface fluctuations appear as parameters which are adjusted to fit the transport data. While the TEM pictures indicated an interfacial boundary which deviated by only one atomic layer, an assumed peak‐to‐peak deviation of approximately five atomic layers is required to fit the experimental mobility. Thus, while the overall comparison of the surface parameters suggests that roughness scattering is a plausible mechanism, close agreement between the theory and experiment is not obtained.

Surface roughness scattering at the Si–SiO2 interface

Surface roughness induced scattering and band tailing

The thermal oxidation of InP in dry oxygen has previously been shown to result in mixed oxide layers, even when grown at pressures as high as 500 atm. This appears to be caused by the slow diffusion of P and O2 through the oxide relative to In. This paper reports on the oxidation of InP in steam at one and 500 atm. Growth in one atm yields an oxide with a composition very similar to those grown in dry oxygen, indicating similar growth kinetics. However, at 500 atm of steam the growth kinetics are changed dramatically and result in a uniform InPO4 layer, suggesting that at high pressure, the H2O diffuses rapidly to the oxide‐InP interface where the oxidation reaction occurs.

High-pressure thermal oxidation of InP in steam

In order to make a viable InP MISFET technology, two major problems remain to be solved: (1) instability in the channel current and (2) variations in the channel mobility with processing. These problems are strongly affected by the chemical and physical structure of the semiconductor/insulator interface. This paper presents results of an investigation of the deposited SiO2/InP interface using XPS, UPS, and ELS combined with transport measurements on special Hall geometry MISFET’s. Physical studies of the SiO2/InP interface using XPS show the presence of a 20–40 A thick native oxide layer primarily composed of InPO4 next to the InP and In2O3 close to the SiO2. UPS and ELS data suggests that the In2O3 forms a trap level slightly above the conduction band. The variation of the channel mobility with surface field and temperature imply that for these devices, the channel mobility is completely dominated by scattering from interface charges and surface roughness, with only a small contribution arising from the bulk optical phonon.

Influence of interfacial structure on the electronic properties of SiO2/InP MISFET’s

The growth of thermal oxides in high pressure dry oxygen has been investigated and compared with oxides grown at 1 atm. The outer layers of the high and low pressure oxides are almost identical but the interfaces are significantly different. The 1 atm oxide interface contains InPO4, In2O3, and elemental P. The high pressure oxide interfaces contain InPO4, In2O3, and P2O5. This suggests that the high pressure causes O2 to diffuse to the interface where it reacts with the P to form P2O5.

R. G. Gann

Papers

Surface roughness scattering at the Si–SiO2 interface

Surface roughness induced scattering and band tailing

High-pressure thermal oxidation of InP in steam

Influence of interfacial structure on the electronic properties of SiO2/InP MISFET’s

High pressure thermal oxide/InP interface