SIS is an interactive tool for synthesis and optimization of sequential circuits Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process It is built on top of MISII [5] and includes all (combinational) optimization techniques therein as well as many enhancements SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits This paper provides an overview of SIS The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays) The second part contains a tutorial example illustrating the design process using SIS

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SIS : A System for Sequential Circuit Synthesis

Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation The package is based on an efficient implementation of the if-then-else (ITE) operator A hash table is used to maintain a strong canonical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure A memory function for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use Memory function efficiency is improved by using rules that detect when equivalent functions are computed The usefulness of the package is enhanced by an automatic and low-cost scheme for recycling memory Experimental results are given to demonstrate why various implementation trade-offs were made These results indicate that the package described here is significantly faster and more memory-efficient than other ROBDD implementations described in the literature

/pdf/efficient-implementation-of-a-bdd-package-2nfh0fbmva.pdf

Efficient implementation of a BDD package

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >

Sequential circuit design using synthesis and optimization

The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed. Combinational logic verification involves checking two networks for functional equivalence. Techniques that flatten networks or use cube enumeration and simulation cannot be used with functions that have very large cube covers. Binary decision diagrams (BDDs) are canonical representations for Boolean functions and offer a technique for formal logic verification. However, the size of BDDs is sensitive to the variable ordering. Ordering strategies based on the network topology are considered. Using these strategies with BDDs, it has been possible to carry out formal verification for a larger set of networks than with existing verification systems. The present method proved significantly faster on the benchmark set of examples tested. >

Logic verification using binary decision diagrams in a logic synthesis environment

A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more in-depth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis of the synthesis methods that have become established as practically significant are provided. Also included are some methods that have theoretical interest and potential for future impact. The discussion covers notation and definitions, representation of the network and nodes, logic decomposition/restructuring, logic optimization/minimization, logic synthesis and testing, and technology mapping. >

Multilevel logic synthesis

An approach is described for the minimization of multilevel logic circuits. A multilevel representation of a block of combinational logic is defined, called a Boolean network. A procedure is then proposed, called ESPRESSOMLD, to transform a given Boolean network into a prime, irredundant, and R-minimal form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Theorems are given that prove the correctness of the proposed procedure. Finally, it is shown that prime and irredundant multilevel logic circuits are 100% testable for input and output single-stuck faults, and that these tests are provided as a byproduct of the minimization. >

Multi-level logic minimization using implicit don't cares

The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples. >

http://ieeexplore.ieee.org/iel2/232/1788/00047144.pdf

BOLD: The Boulder Optimal Logic Design system

The authors present a number of results exploring the relationship between algebraic transformations for area optimization and the testability of combinational logic circuits They show that for each multifault in an algebraically factored circuit there is an equivalent multifault in the original circuit, and it is well known that two-level single-output circuits that are single-fault testable are also multifault testable They also show how these results imply that algebraic factorization may be applied to minimized (and therefore completely single-fault testable) two-level circuits, in order to synthesize area optimized, completely multifault testable circuits Furthermore, when algebraic factorization is applied to a minimized two-level circuit all tests needed for complete multifault coverage of the synthesized circuit can be derived from the single-fault tests for the original two-level circuit >

On properties of algebraic transformation and the multifault testability of multilevel logic

A description is given of a theory for, and the application of, a general algorithm for determining whether a given multilevel Boolean function is a tautology or whether two given multilevel Boolean functions are equivalent. Four specific cases of this general algorithm are examined. These are termed the flattening method, the don't-care method, the simulation method, and the algebraic string comparison method. A single unifying algorithm frame is given for the implementation of any of these four methods, depending on parameterization. Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others. The primary application of these algorithms is as a verification tool for silicon compilation systems. However, these algorithms are also being used as the foundation for multilevel logic minimization and automatic test pattern generation programs. >

Verification algorithms for VLSI synthesis

Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the two cornerstone tools of the BOLD system, ESPRESSOMLT (multilevel logic minimizer based on tautology checking) and MLTAUT (multilevel logic verifier). The relationship between the implied values and the intermediate don't care set is presented. Then it is shown how this relationship can be exploited to reduce the number of tautology calls and the number of leaves in the binary recursion tree of tautology checking. A parallelized version MLTAUT2P, which runs on a Sun 3/75 LAN, is discussed. ESPRESSOMLT2, is expected to have speedups of up to a factor of 20 and the parallelized version a factor of over 100. >

R. Jacoby

Papers

Multi-level logic minimization using implicit don't cares

BOLD: The Boulder Optimal Logic Design system

On properties of algebraic transformation and the multifault testability of multilevel logic

Verification algorithms for VLSI synthesis

Performance enhancements in BOLD using 'implications'