In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high- $k$ dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio $(\sim 6\times 10^{8})$ , a point subthreshold slope (SS) of ${\sim}{\rm 38}~{\rm mV}$ /decade, and an average SS of ${\sim}{\rm 70}~{\rm mV}$ /decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.

Junctionless Tunnel Field Effect Transistor

This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs). After introducing the classification and the terminology used in this paper, we firstly present the basis of the different transport models used in device-level simulation (drift-diffusion, hydrodynamic, Monte-Carlo and some approximated and exact quantum-mechanical based approaches). We also focus on the main emerging physical phenomena affecting ultra-short MOSFETs (quantum effects, tunneling current, ballistic operation) and the methods envisaged for taking them into account at device simulation level. Several examples of device simulation are given at the end of this first part, including recent results on fully-depleted SOI and multiple-gate devices. In the second part, we briefly survey the different circuit-level modeling approaches (circuit-level simulation, Mixed-Mode, 3-D simulation of portions of circuits) of single-event effects in integrated circuits. The SEU in advanced SRAM and SEE mechanisms in logic circuits are reminded. The production and propagation of digital single-event transients (DSETs) in sequential and combinational logic, as well as the soft error rate trends with scaling are particularly addressed. Recent bibliographical examples of simulation in SRAMs and logic circuits are presented and discussed to illustrate these topics at circuit-level.

Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

The charge distribution at the semiconductgor-insulator interface is calculated for electrons by solving Schrodinger's and Poisson's equations self-consistently for particles obeying Fermi-Dirac statistics at 300 K. The results are applied to carriers in the channel of a crystalline MOSFET with the (100) axis perpendicular to the gate oxide. The inversion charge density calculated quantum mechanically is smaller than that calculated classically. This affects the shift of the subthreshold curves. The shift is larger at higher substrate impurity concentrations, and is especially pronounced at more than 10 17 cm −3 , which is the concentration used in recent MOS devices. The shift is as large as 0.18 V when the substrate impurity concentration is 8.5 × 10 17 cm −3 . Comparisons with measurement are also shown and it agrees well with quantum mechanical calculations. The inversion layer depth is compared, and a new efficient method is derived by transferring the quantum mechanical effect into the classical calculation. The results of this new method agree well with the quantum mechanical calculations and with the measurements.

Quantum effects in Si n-MOS inversion layer at high substrate concentration

The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

Successful scaling of MOS device feature size requires thinner gate oxides and higher levels of channel doping in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. However, in deep submicron (/spl les/0.25 /spl mu/m gate length) technology, the combination of the extremely thin gate oxides (t/sub ox//spl les/10 nm) and high channel doping levels (/spl ges/10/sup 17/ cm/sup -3/) results in transverse electric fields at the Si/SiO/sub 2/ interface that are sufficiently large, even near threshold, to quantize electron motion perpendicular to the interface. This phenomenon is well known and begins to have an observable impact on room temperature deep submicron MOS device performance when compared to the traditional classical predictions which do not take into account these quantum mechanical effects. Thus, for accurate and efficient device simulations, these effects must be properly accounted for in today's widely used moment-based device simulators. This paper describes the development and implementation into PISCES of a new computationally efficient three-subband model that predicts both the quantum mechanical effects in electron inversion layers and the electron distribution within the inversion layer. In addition, a model recently proposed by van Dort et al. (1994) has been implemented in PISCES. By comparison with self-consistent calculations and previously published experimental data, these two different approaches for modeling the electron inversion layer quantization are shown to be adequate in order to both accurately and efficiently simulate many of the effects of quantization on the electrical characteristics of N-channel MOS transistors.

A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs

We present a rigorous investigation of carrier transport near the semiconductor-insulator interface of a MOSFET. Deriving a new current equation we include the quantum mechanical correction on the carrier density distribution near the interface. This equation also contain a new mobility model for the surface field reduced channel mobility, that is derived from Boltzmann's equation. We implemented this new equation into the device simulator MINIMOS and discuss its consequences to real devices.

Carrier transport near the Si/SiO2 interface of a MOSFET

For self-aligned bipolar technologies the sidewall region under the residual spacer, which is very much influenced by the spacer geometry, is a key feature. We have investigated the effect of the spacer geometry on the transistor performance, especially on the current gain β. The spacer geometry is arranged by varying its width separating the n + and p + lateral diffusions and by varying its depth penetrating into the monocrystalline silicon. It has been found that these two variations do not cause the same effect on β. Although the increase of both the spacer isolation depth and width causes an increase in β, β has an enhanced dependence on the spacer depth. This latter finding sets a limitation on the maximum spacer depth for the high performance bipolar transistors. A 2-D simulation is performed to demonstrate these effects.

Dependence of current gain β on spacer geometry and emitter size in polysilicon self-aligned bipolar transistors

The influence of quantum mechanical corrections of particle density near the Si/SiO 2 interface on the channel mobility of a MOSFET is investigated by an approximation of the quantum statistical expectation values and by an exact solution of Schrodinger's equation perpendicular to the interface. A new model for mobility reduction at the interface is derived. The model is implemented in the device simulator MINIMOS, the results show good agreement with n-and p-channel devices of the 4M-DRAM generation.

https://ieeexplore.ieee.org/iel5/5436369/5436370/05436508.pdf

R. Kircher

Papers

Carrier transport near the Si/SiO2 interface of a MOSFET

Dependence of current gain β on spacer geometry and emitter size in polysilicon self-aligned bipolar transistors

Charge Transport Near the Si/SiO 2 Interface in MOSFET Devices