Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

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1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

InP-Based Transistor Fabrication

Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Tri-gate field-effect transistors formed by aspect ratio trapping

Advances in nanomechanical structures and thermal-emission devices have provided fresh perspectives for the development of infrared thermal detectors. Joseph Talghader and colleagues at the University of Minnesota, USA, review fundamental and technological progress in the field from the perspective of spectrally selective detection, which is important for applications ranging from chemical detection and target recognition to studies in cavity quantum electrodynamics. Placing emphasis on devices operating at non-cryogenic temperatures, Talghader et al. discuss basic and practical aspects of detectors based on both natural and artificial materials. They round off their discussion by looking at current trends in material science and imaging technology to speculate about the future directions of the field.

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Spectral selectivity in infrared thermal detection

We report a resonant cavity Si photodiode grown by merged epitaxial lateral overgrowth. At a reverse bias of 5 V, the dark current was 2.7 pA and the bandwidth exceeded 34 GHz. The peak quantum efficiencies ranged from 42% at 704 nm to 31% at 836 nm. This is the highest speed reported for a Si p-i-n photodiode and the highest bandwidth-efficiency product for any Si-based photodetector.

Resonant-cavity-enhanced high-speed Si photodiode grown by epitaxial lateral overgrowth

We compare monolithic silicon optical receivers fabricated on high resistivity and silicon-on-insulator (SOI) substrates. Each receiver consisted of a lateral p-i-n photodiode and an NMOS transimpedance preamplifier. At a drain voltage (V/sub DD/) of 3.5 V, a photodiode voltage (V/sub PD/) of 30 V, and a wavelength of 850 nm, the high resistivity receiver exhibited sensitivities of -31.9 dBm at 622 Mb/s and -23.2 dBm at the maximum operating speed of 1.0 Gb/s. At V/sub DD/=5 V and V/sub PD/=20 V, the sensitivity of the SOI receiver was -26.1 dBm at 622 Mb/s, -20.2 dBm at 1.0 Gb/s and -12.2 dBm at the maximum speed of 2.0 Gb/s. Single supply operation at 5 V and 3 V was also demonstrated for the SOI receiver. Methods for extending the speed and improving the sensitivity characteristics in more advanced technologies with lower supply voltages are discussed.

High-speed monolithic silicon photoreceivers on high resistivity and SOI substrates

We report a monolithically integrated optical receiver fabricated on an SOI substrate. The receiver consists of a lateral p-i-n photodiode and an NMOS transimpedance preamplifier. At V/sub DD/=5 V, the receiver dissipated 37 mW of power with a typical transimpedance gain of 49 dB./spl Omega/. At operating speeds of 622 Mb/s and 1.0 and 2.0 Gb/s, the receiver achieved a bit error ratio of 10/sup -9/ at received powers of -31.6, -25.7, and -17.7 dBm, respectively.

A high-speed monolithic silicon photoreceiver fabricated on SOI

We report high-speed interdigitated (nonmetalized) p-i-n Si photodiodes fabricated on SOI substrates that operate at low bias voltages and that offer easy integration with transistor fabrication processes. Devices fabricated with a finger spacing of 2 /spl mu/m and a 3.75-/spl mu/m-thick active layer achieved a 1.1-GHz bandwidth at a bias of -3 V with a peak efficiency of 29% (0.2 A/W) at 850 nm. Photodiodes with the same geometry that were fabricated on a 2.71-/spl mu/m-thick active layer exhibited a 3.4-GHz bandwidth and a quantum efficiency of 24% (0.16 A/W) at 840 nm when biased at -3 V. The dark current of the photodiodes was less than 25 pA at -3 V, and the capacitance of the photodiodes was less than 265 fF at an applied bias of -3 V.

Design and implementation of high-speed planar Si photodiodes fabricated on SOI substrates

Previously, it has been shown that the bandwidth of Si photodiodes can be increased by more than an order of magnitude, without sacrificing responsivity, by a resonant-cavity structure that utilized GeSi-Si asymmetric Bragg reflectors. In this letter, we report an interdigitated p-i-n polysilicon resonant-cavity photodiode, which employs a Si-SiO/sub 2/ Bragg reflector, that is more compatible with standard Si processing technology. For an absorbing region thickness of only 0.5 /spl mu/m, a peak quantum efficiency of 40% was achieved and the dark current was <60 nA at 10 V. For 2 /spl mu/m/spl times/2-/spl mu/m finger width and spacing the bandwidth was 10 GHz.

R. Li

Papers

Resonant-cavity-enhanced high-speed Si photodiode grown by epitaxial lateral overgrowth

High-speed monolithic silicon photoreceivers on high resistivity and SOI substrates

A high-speed monolithic silicon photoreceiver fabricated on SOI

Design and implementation of high-speed planar Si photodiodes fabricated on SOI substrates

High-speed polysilicon resonant-cavity photodiode with SiO/sub 2/-Si Bragg reflectors