The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V/sub th/ as a function of L/sub eff/, V/sub DS/, V/sub BS/, and pocket parameters down to 0.1-/spl mu/m channel length. The new model shows that the V/sub th/ roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N/sub p/)/sup 1/4 /L/sub p/. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L/sub min/ is presented. The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed.

Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's

The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects (SCEs) [drain-induced barrier-lowering (DIBL) and channel-length modulation (CLM)] and, more importantly, these unique features could be controlled by engineering the material and length of the gate. This work demonstrates a new way of engineering ultrasmall transistors and provides the incentive and guide for experimental exploration.

/pdf/exploring-the-novel-characteristics-of-hetero-material-gate-3pz5pdn7y7.pdf

Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering

Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance

https://web.iitd.ac.in/~mamidala/HTMLobj-168/MEJ_sept04.pdf

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

A unified compact threshold voltage model is developed, which accounts for the normal and reverse short-channel effects with full range of body- and drain-bias conditions, and has been verified with experimental data down to 0.18 /spl mu/m. The model only has five process-dependent fitting parameters with a simple one-iteration extraction procedure, and can be correlated to process variables for aiding new deep-submicron technology development. The approach to the model formulation is original and general, and can be extended to other key device performance parameters.

A general approach to compact threshold voltage formulation based on 2D numerical simulation and experimental correlation for deep-submicron ULSI technology development [CMOS]

Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel. >

R.S. Bass

Papers

A model for anomalous short-channel behavior in submicron MOSFETs