R
Rajesh Mehra
Researcher at Panjab University, Chandigarh
Publications - 178
Citations - 1331
Rajesh Mehra is an academic researcher from Panjab University, Chandigarh. The author has contributed to research in topics: Field-programmable gate array & CMOS. The author has an hindex of 16, co-authored 178 publications receiving 936 citations.
Papers
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Journal ArticleDOI
Breast cancer histology images classification: Training from scratch or transfer learning?
Shallu,Rajesh Mehra +1 more
TL;DR: The ability of transfer learning in comparison with the fully-trained network on the histopathological imaging modality is demonstrated by considering three pre-trained networks: VGG16, VGG19, and ResNet50 and analyzed their behavior for magnification independent breast cancer classification.
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Conventional Machine Learning and Deep Learning Approach for Multi-Classification of Breast Cancer Histopathology Images—a Comparative Insight
Shallu Sharma,Rajesh Mehra +1 more
TL;DR: The results reveal that the use of pre-trained networks as feature extractor exhibited superior performance in contrast to baseline approach and handcrafted approach for all the magnifications, and it has been observed that the augmentation plays a pivotal role in further enhancing the classification accuracy.
Analysis of Power Spectrum Estimation Using Welch Method for Various Window Techniques
Pranay Kumar Rahi,Rajesh Mehra +1 more
TL;DR: The PSE based on both Rectangular as well as Hamming window has been designed and simulated using MATLAB and it can be observed that the Rectangular and Hamming give better results than other windows like Bartlett, Hanning and Blackman window.
Journal ArticleDOI
Device simulation of lead-free MASnI3 solar cell with CuSbS2 (copper antimony sulfide)
Chandni Devi,Rajesh Mehra +1 more
TL;DR: In this paper, a planar heterojunction design of Sn-based iodide perovskite PSC is proposed, where the copper antimony sulfide (CuSbS2) is used for the very first time as hole transport layer (HTL) in conjunction with the MASnI3 active layer in this design.
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Leakage Power Reduction in CMOS VLSI Circuits
Pushpa Saini,Rajesh Mehra +1 more
TL;DR: New methods have been proposed for the leakage power reduction in 90nm technology and the proposed methods will be compared with the previous existing leakage reduction techniques and the result is simulated using Microwind 3.1.