A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, and stored in the latch responsive to the clock signal. The digital signal stored in the latch is evaluated to determine if the stored digital signal has an expected value. The timing offset of the digital signal is thereafter adjusted relative to the clock signal. and the digital signal is once again stored in the latch responsive to the clock signal at the new timing offset. A number of digital signals at respective timing offsets relative to the clock signal are stored and evaluated, and a final timing offset of the digital signal is selected from the ones of the timing offsets that cause the latch to store the digital signal having the expected value. The timing offset of the digital signal is thereafter adjusted to the selected final timing offset. A read synchronization circuit may adaptively adjust the timing offset of digital signals in this manner, and such a read synchronization circuit may be utilized in many types of integrated circuits, including packetized dynamic random access memories, memory systems including a memory controller and one or more such packetized dynamic random access memories, and in computer systems including a plurality of such packetized dynamic random access memories.

Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Integrated chip package structure using organic substrate and method of manufacturing the same

A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and command busses. Each memory module includes the vernier clock adjustment circuitry.

Clock vernier adjustment

A 4.9-6.4-Gb/s two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer (FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has been designed in 0.13-/spl mu/m CMOS. The transmitter features a total jitter (TJ) of 35 ps p-p at 10/sup -12/ bit error rate (BER) and can output up to 1200 mVppd into a 100-/spl Omega/ differential load. Low jitter is achieved through the use of an LC-tank-based VCO/PLL system that achieves a typical random jitter of 0.6 ps over a phase noise integration range from 6 MHz to 3.2 GHz. The receiver features a variable-gain amplifier (VGA) with gain ranging from -6to +10dB in /spl sim/1dB steps, an analog peaking amplifier, and a continuously adapted DFE-based data slicer that uses a hybrid speculative/dynamic feedback architecture optimized for high-speed operation. The receiver system is designed to operate with a signal level ranging from 50 to 1200 mVppd. Error-free operation of the system has been demonstrated on lossy transmission line channels with over 32-dB loss at the Nyquist (1/2 Bd rate) frequency. The Tx/Rx pair with amortized PLL power consumes 290 mW of power from a 1.2-V supply while driving 600 mVppd and uses a die area of 0.79 mm/sup 2/.

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

Clock data recovery circuitry associated with programmable logic device circuitry

Phase-locked loops (PLL) are widely used for clock-phase synchronization, frequency synthesis and clock distribution It is highly desirable that the standard digital CMOS process be used in the PLL design because process modifications increase product cost Other desirable features include insensitivity to noise and a fully integrated design The PLL design reported in this paper has all the above features A standard digital CMOS process is used to produce a fully differential structure that is immune to substrate and supply noise The PLL function includes multiplication of frequency and synchronization of input and output clock phases The architecture is unique because resistors are not needed for PLL loop stabilization

Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter

An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor. This second layer of metal may also be used to form inductors. Moreover both inductors and resistors can be formed; however this may require a third layer of metal for connection purposes.

Integrated compact capacitor-resistor/inductor configuration

A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.

Integrated circuit chip having built-in self measurement for PLL jitter and phase error

A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

Programmable low-power high-frequency divider

A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition. The circuits for these components are described in detail.

Ram Kelkar

Papers

Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter

Integrated compact capacitor-resistor/inductor configuration

Integrated circuit chip having built-in self measurement for PLL jitter and phase error

Programmable low-power high-frequency divider

Method and apparatus for reducing jitter in a phase locked loop circuit