Showing papers by "Rao Tummala published in 2000"

Next generation integral passives: materials, processes, and integration of resistors and capacitors on PWB substrates

Abstract: Integral passives are becoming increasingly important in realizing next generation electronics industry needs through gradual replacement of discretes. The need for integral passives emerges from the increasing consumer demand for product miniaturization thus requiring components to be smaller and packaging to be space efficient. In this paper, the feasibility of integration of polymer/ceramic thin film (∼5 μm thick) capacitors (C) with other passive components such as resistors (R) and inductors (L) has been discussed. An integrated RC network requiring relatively large capacitance and resistance is selected as a model for co-integration of R and C components using low temperature PWB compatible fabrication processes. This test vehicle is a subset of a large electrical circuit of a functional medical device. In order to produce higher capacitance density and reduce in-plane device area, multi-layer (currently two-layer) capacitors are stacked in the thickness direction. A commercially available Ohmega-Ply resistor/conductor material is selected for integral resistors. Resistors were fabricated using a multi-step lithography process with the utilization of two separate masks. Bottom copper electrodes for capacitors were also defined during the resistor fabrication process. Photodefinable epoxies filled with a high permittivity ceramic powder were used for fabrication of thin film capacitors. Epoxy and ceramic powders were mixed in the required proportion and blended using a high shear apparatus. The coating solution was homogenized in a roll miller for 3 to 5 days prior to casting in order to prevent settling of the higher density ceramic particles. Capacitors were fabricated by spin-coating on the sub-etched copper electrodes. The deposited dielectric layers were dried, exposed with UV radiation, patterned, and thermally cured. Top capacitor electrodes (copper) were deposited using a metal or an e-beam evaporator. The electrodes were patterned using the standard photolithography processes. Selected good samples were used for depositing the second capacitor layer. The RC network is extended to incorporate electroplated polymer/ferrite core micro-inductors through the fabrication of an industry prototype low pass RLC filter. Meniscus coating was evaluated for large area manufacturing with high process yield. A capacitance density of ∼3 nF cm−2 was obtained on a single layer capacitor with ∼6 μm thick films. The capacitance density was increased to ∼6 nF cm−2 with the two-layer deposition process. The capacitors were relatively stable up to a frequency range of 120 Hz to 100 KHz. Meniscus coating was qualified to be a viable manufacturable method for depositing polymer/ceramic capacitors on large area (300mm x 300mm) PWB substrates. Dielectric constant values in the range of 3.5 to 35 with increase in filler loading up to 45 vol% were achieved in the epoxy nanocomposite system where the dielectric constant of the host polymer was limited to ∼3.5. Higher dielectric constant polymers are required to meet the increasingly higher capacitance needs for the next generation electronics packaging. Possible avenues for achieving higher capacitance density in polymer/ceramic nanocomposite system have been discussed.

Numerical and experimental investigations of large IC flip chip attach

Abstract: Because flip chips can achieve high electrical interconnect speed, high density, and low profiles, a team from the Fraunhofer Institute for Reliability and Microintegration in Berlin and from Georgia Tech undertake a study examining the extreme limits of flip chip input/output (I/O) capabilities and physical dimensions. Their starting point is a SIA estimate of memory requirements, based on Moore's Law, for the year 2012. In order to study the limitations of flip chip technology the groups are working on both, advanced thermomechanical simulation and hands-on interconnection technology resulting in the design of four flip chips. They have the dimensions of 10/spl times/10 mm/sup 2/, 20/spl times/20 mm/sup 2/, 30/spl times/30 mm/sup 2/, and 40/spl times/40 mm/sup 2/. With these designs both, the simulation and the interconnection technology departments of Fraunhofer IZM start to evaluate the feasibility of flip chips beyond 20/spl times/20 mm/sup 2/.

Multi-layer fully organic-based system on package (SOP) technology for RF applications

Abstract: We present the development and characterization of multi-layer fully organic-based system-on-package (SOP) technology, referred to as the single level integrated module (SLIM), for RF applications. A multi-layer transceiver architecture and a hybrid microstrip and coplanar waveguide interconnect scheme have been proposed and developed to allow high density interconnects. Coplanar waveguide transmission line test structures have been fabricated on the multi-layer material system and demonstrate an insertion loss of 1.4 dB/in at 13 GHz and a return loss better than 15 dB at 13 GHz.

Fabrication of a Fully Integrated Passive Module for Filter Application Using MCM-D Compatible Processes

Abstract: Integral passive is an emerging technology which is currently perceived as a possible alternative to the discrete passive technology in fulfilling the next generation packaging needs. Although discrete surface mount passive components (resistors, capacitors, and inductors) have been well characterized, the development of integral passive components suitable for co-integration on the board level is relatively recent. Since in some applications the number of passive components can exceed the number and the area of IC chips on a circuit board or in a package, such integration of passive components would be necessary to substantially eliminate part count and reduce device area. To address these issues, integration technology for passive elements in the same manner as for transistors is necessary. In addition, the fabrication sequence of all integral passive components should be mutually compatible for co-integration on the same substrate. In this paper, materials and fabrication issues for passive elements such as resistors (R), capacitors (C), and inductors (L) and the feasibility of integration of these fabricated passive components on glass substrates have been addressed. An active filter circuit has been selected for a case study for R, L, and C co-integration. This passive module contains eleven resistors, four capacitors, and four inductors, and is fabricated using MCM-D (multichip module-deposited) compatible processes. A variety of materials appropriate for fabrication of integral passives in a mutually compatible fashion were investigated, including chromium and nickel-chromium resistors, composites of high dielectric constant materials in epoxies for capacitor dielectrics, and composites of magnetic ferrite particles in polyimides for inductor core and shielding. The fabricated devices showed good agreement between the design values and the corresponding measured values. It is anticipated that some of these materials and fabrication processes can be implemented for the MCM-L (multichip module-laminate) compatible packaging. © 2000 Kluwer Academic Publishers

PWB compatible high value integral capacitors by MOCVD

Abstract: The 1998 National Electronics Manufacturing Technology Roadmap indicates that a capacitance density of ∼50 nF cm−2 will be required in 2001 for successful implementation of integral passive technology in the microelectronics packaging industries. Higher permittivity polymer/ceramic nanocomposites have been proven to be a viable option for integral capacitors on printed wiring boards (PWB). Although the nanocomposite materials are in their developmental stage, it is unlikely that this materials system could meet such high capacitance needs and still utilize a large area manufacturable process. In this study, an alternative metal organic chemical vapor deposition (MOCVD) technique has been implemented to deposit TiO2 thin film dielectrics at temperatures below 180 °C with higher capacitance densities. Two different metal-dielectric-metal type parallel plate capacitor structures have been fabricated on silicon and PWB substrates for relatively high frequency (45 MHz–1 GHz) and low frequency (100 Hz–1 MHz) characterization. Copper was used as the ground and upper electrodes with a 10 nm Cr adhesion layer between the dielectric and the electrodes. Capacitance was measured using a Keithley LCZ meter and a HP4194 impedance gain-phase analzer at the lower frequency range. Specific capacitance as high as 200 nF cm−2 was achieved at 1 MHz from devices built on silicon substrates and at 100 kHz from devices on PWB substrates. For the first time, thin film TiO2 on PWB substrates is reported at temperatures below 180 °C using MOCVD.

Ultra-fine photoresist image formation for next generation high-density PWB substrate

Abstract: System-on-a-Package (SOP) is fast becoming a primary key towards the drive for integration of mixed technologies such as Rf, digital, analog, MEMS and optical at the electronic package level. A key enabler of this technology is a fully integrated substrate, called Single Level Integrated Module (SLIM), with very high wiring density and integrated passive and optoelectronic components. This paper presents an overview of the SLIM testbed integration process and test vehicles, with particular emphasis on ultra-fine resist lithography and microvia processing. This paper will focus on the issues, challenges and results for achieving very fine line and ultra fine line image formation on fiberglass reinforced epoxy substrates for next generation electronic packages. Four commercial photo-resist materials were evaluated for their imaging resolution. The exposure and development processes have been optimized and several related effects, which limit the fine line imaging, have been investigated. Line widths down to 7.5 μm have been achieved at the Packaging Research Center (PRC) on PWB substrates using low cost liquid photoresist and associated processes over a large area.

Evaluation of carbon-filled polymer composites for future base substrate and integral resistor applications

Abstract: Future packaging with multi-layered high-density wiring and direct-chip-attach requires substrates having superior thermomechanical properties such as no CTE mismatch with the attached IC chip and high stiffness. Various novel polymer composites were evaluated in this work and compared to the conventional FR-4 substrates in order to assess their candidature for future base substrate applications. Carbon cloth, milled fibers and nanofibers have many attractive properties such as negative CTE, high modulus and were hence pursued in this work. The manufactured carbon-polymer composites showed CTE in the range 2-3 ppm/K and significant improvement in stiffness (50 GPa at only 36 vol. % loading). In related work, polymer composites with carbon black and conductive carbon nanofibers were evaluated for embedded resistor applications. Resistivities in the range of 0.2 - 1.5 Ohm cm were obtained. These composites show lot of potential for future electronic packaging applications both by simplifying the build-up process and eliminating the underfill materials.

Low-cost large area processing using small area substrates-a novel multitiled palletization concept for MCM-D thin film process

Abstract: Multichip module-deposited (MCM-D) has been the solution for integrated high density packaging due to its superior line resolution and higher inputs/outputs (I/O) density compared to MCM-C and multichip module-laminate (MCM-L) technologies. However the consumer demand for high performance products at reduced costs is ever increasing, and this trend is expected to continue in the 21st Century. In order to find a low-cost solution for future MCM-D packaging, a novel palletization process which incorporates several tiles (alumina or silicon) on a large carrier glass (pallet) has been established in this study. The multitiling format provides simultaneous processing of several small tiles onto a re-usable CTE matched carrier glass. The tiles are attached to the glass with a low modulus adhesive that can be released at an elevated temperature (/spl sim/450/spl deg/C). The objective of this study is to develop a multitiling process for a 300 mm/spl times/300 mm area that is scalable up to 600 mm/spl times/600 mm format. There are several challenges in realization of the large area palletization approach, such as formulation and qualification of a high temperature reworkable adhesive and minimization of out-of-plane warpage of the tiled assembly. Finite element models for warpage and its validation by shadow moire measurement, formulation of a compliant adhesive for thermal stability up to 400/spl deg/C are reported in previous publications. This paper deals with (1) the validation of the palletization concept on a 300 mm x 300 mm glass with weight restriction below 3 lbs and thickness limitation to <6.25 mm, and (2) qualification of the formulated adhesive through a correlative study on high temperature detachability of the attached tiles, chemical compatibility of the adhesive with acids, bases, and less polar solvents, and interfacial shear strength at the lass/adhesive/tile joints. MCM-D thin film process on the tiled substrates is to be conducted by the member companies of the MCM-D Consortium.

st Polymers for electronic packaging in the 21 century

Abstract: The next generation of polymeric materials for electronic packaging requires high performance, such as high T g , low loss, low dielectric constant for high frequency (in excess of 100 GHz for wireless and portable products), which are described in this chapter. Nanostructure air gap ultra-low dielectrics are developed. Furthermore, photo-definable with positive-tone materials for ease of process are needed for IG dielectric as well as sequential build-up high density PWB technology applications. High dielectric polymer composites (in excess of 100–200) with nanostructure inorganic filler will be needed for the capacitor application of building imbedded passives. Conductive polymers with high current density, high toughness, and low conductivity fatigue will be needed for ultra fine-pitch replacements for solder joint interconnects. The electronics consumer will depend on all these materials that will be multifunctional, high performance, yet low cost. It is a challenge that all chemists, materials scientists, and chemical engineers will face in the 21st century.

Delamination issues in integration of highly filled polymer-ceramic nanocomposite films on MCM-L compatible substrates

Abstract: The National Electronics Manufacturing Technology roadmap indicates that a capacitance density of 50 nF/cm/sup 2/ will be required in 2001 for successful implementation of integral passive technology. Polymer-ceramic composites are a favorable choice for thin-film capacitors in low-temperature MCM-L technology. Improvement in dielectric properties of the material, achievement of thin and defect-free films and integration on to large area substrates form the cornerstones for this technology. The Packaging Research Center at Georgia Tech. has been actively involved in achieving improved dielectric properties by developing high solids loading and well-dispersed suspensions based on colloidal techniques. The integration of thin-film composites into the subsequent fabrication process becomes increasingly challenging with higher filler content. For example, delamination of the composite from the bottom copper layer has been consistently observed during the modification of composite surface for increasing the adhesion between the electroless copper deposit (top electrode) and composite surface. The surface modification typically involves an etch-treatment with a powerful oxidizing agent such as permanganate. This delamination was not observed in fully cured neat epoxies. The role of fillers in preventing the curing of the epoxy, the reactions between permanganate and uncured epoxy and the lack of adhesion between ceramic and bottom electrode are some of the key issues involved in this delamination problem. This is further complicated by the classic copper-epoxy de-adhesion problem originating from the copper oxide film at the copper-epoxy interface. This work presents our investigation of the origin of this delamination problem by delineating these issues and identifying the key effects. In particular, the role of epoxy curing and filler content based on the interface and epoxy characterization is addressed here. A failure mechanism is proposed from the correlation between epoxy cure and the delamination during etch treatment.

Evaluation and characterization of high-performance filling encapsulants for system chips application

Abstract: An innovative Precisely Interconnected Chips (PIC) technology is currently under development at IBM to seek more effective means of creating system chips. This development focuses on developing fabrication methods to permit the realization of high yielding large area chips, as well as chips that may contain very diverse technologies. Another focus is to realize system chips which have their basic chip characteristics compromised as is the case in many of today's system chip concepts. This paper reports on the use of a high performance filling encapsulant based on epoxy resin, which is used to connect the different chip sector macros that make up the system chip. This novel encapsulant remains thermally stable through the subsequent processing temperature hierarchies during the system chips fabrication. Spherical SiO/sub 2/ powders (with special morphology and size distribution) are incorporated into the epoxy resin to improve its mechanical properties, reduce coefficient of thermal expansion, and increase thermal conductivity. Adhesion and rheological properties of the formulated materials are evaluated. Microstructure of the filled Epoxy system is investigated to confirm the thermal reliability of the encapsulants. The formulated EPOXY A resin is qualified for manufacturing process based on the filling process, mechanical integrity, and thermal reliability.