This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Customizable and programmable cell array

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Method of time multiplexing a programmable logic device

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM

A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Devices and methods with programmable logic and digital signal processing regions

A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiments, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.

Time multiplexed programmable logic device

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations. In another embodiment, a CLB includes four LMCs and a multiplier circuit such that large amounts of logic are locally implemented, thereby avoiding signal delays associated with transmission over general purposed interconnect resources within a PLD.

Fpga configurable logic block with multi-purpose logic/memory circuit

A PLD is operable in a variety of modes. In a first mode, the timeshare mode, the PLD remains at a single configuration for a plurality of user clock cycles. In a second mode, the logic engine mode, the PLD sequences through multiple configurations for each user cycle. In this mode, the period of time during which a configuration is active is called a micro cycle. In a third mode, the static mode, multiple configurations are programmed identically, so that the PLD performs the same function regardless of the configuration. Finally, the PLD is also operable in a combination mode, wherein part of the chip operates in one mode, for example, the static mode, and another part of the chip operates in the logic engine mode or the timeshare mode. In an alternative or co-existing embodiment, the PLD operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.

Configuration modes for a time multiplexed programmable logic device

In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage. The inactive storage is accessible for read or write operations by the active configuration by a structure comprising: a core including a plurality of configurable elements selectively coupled to each other, a memory controller for controlling the memory that configures the logic and routing in accordance with the active configuration, a command register to hold commands for the memory controller, a memory address register to address the memory, and a memory data register coupled to the memory and the plurality of combinational elements. In one embodiment, the array of the present invention includes a configurable routing structure for providing the active configuration access to the memory address register, the memory data register, and the command register. The configurable routing structure is generally controlled by signals from the user logic, thereby significantly increasing user flexibility in using the programmable array.

Richard A. Carberry

Papers

Method of time multiplexing a programmable logic device

Time multiplexed programmable logic device

Fpga configurable logic block with multi-purpose logic/memory circuit

Configuration modes for a time multiplexed programmable logic device

Programmable logic device with hierarchical confiquration and state storage