Patent
Method of time multiplexing a programmable logic device
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TLDR
In this paper, the authors propose to assign at least one slice of a programmable logic device (PLD) to user data memory and enable disabling access to at least N memory cells.Abstract:
A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.read more
Citations
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Method for creating circuit redundancy in programmable logic devices
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Martin Vorbach,Robert Münch +1 more
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TL;DR: In this paper, a data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses or communication lines operated at a second clock rate is described.
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Computer-implemented method of optimizing a time multiplexed programmable logic device
TL;DR: In this paper, a computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle.
References
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Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
Patent
Programmable logic cell and array
TL;DR: An improved programmable logic cell (1) as discussed by the authors is a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b, 8a, 8b) and another to its right (or, to the East) (5a, 5b, 9a, 9b, 10b, 11a, 12b), one above (or below) (2a, 2b, 6a, 6b), and one below (
Patent
Configurable logic element
TL;DR: A configurable logic circuit achieves versatility by including a configurable combinational logic element, configurable storage circuit, and configurable output select logic as discussed by the authors, which can be configured to operate as a D flip flop, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector.
Patent
Programmable application specific integrated circuit and logic cell therefor
TL;DR: The logic cell as discussed by the authors is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
Proceedings ArticleDOI
DPGA-coupled microprocessors: commodity ICs for the early 21st Century
TL;DR: It is noted how the tight integration of reconfigurable logic into the processor can overcome some of the major limitations of contemporary attached reconfiguring computer engines.