Showing papers by "Richard Lai published in 2016"

An MMIC Low-Noise Amplifier Design Technique

Abstract: In this paper we discuss the design of low-noise amplifiers (LNAs) for both cryogenic and room-temperature operation in general and take the stability and linearity of the amplifiers into special consideration. Oscillations that can occur within a multi-finger transistor are studied and verified with simulations and measurements. To overcome the stability problem related to the multi-finger transistor design approach a parallel two-finger unit transistor monolithic microwave integrated circuit LNA design technique, which enables the design of wideband and high-linearity LNAs with very stable, predictable, and repeatable operation, is proposed. The feasibility of the proposed design technique is proved by demonstrating a three-stage LNA packaged in a WR10 waveguide housing and fabricated using a 35-nm InP HEMT technology that achieves more than a 20-dB gain from 75 to 116 GHz and 26–33-K noise temperature from 85 to 116 GHz when cryogenically cooled to 27 K.

Miniature packaging concept for LNAs in the 200–300 GHz range

Abstract: In this work, we describe new miniaturized low noise amplifier modules which we developed for incorporation in small-scale satellites or Cubesats, and which exhibit similar or better performance compared to previously reported LNAs in the literature. We have targeted the WR4 (170–260 GHz) and WR3 (220–325 GHz) waveguide bands for the module development. The modules include two different methods of E-plane probes which have been developed for low loss, and stability at high frequencies. MMIC LNAs were also developed for these frequency ranges and fabricated in Northrop Grumman Corporation's 35 nm InP HEMT technology, and we have experimentally verified that noise performance is lower than reported in prior work. The best results include a miniature LNA module with 550K noise at 224 GHz, and a wideband LNA module with 15 dB gain from 230–280 GHz.

Cryogenic low noise MMIC amplifiers for U-Band (40–60 GHz)

Abstract: In this work, we describe monolithic millimeter-wave integrated circuit (MMIC) Low Noise Amplifier (LNA) and mixer designs for U-Band, also known as the WR19 waveguide band (40–60 GHz). The LNAs were fabricated in NGC's 35 nm InP HEMT MMIC process. The MMICs were packaged in WR19 waveguide housings and tested for noise, both at room temperature and cryogenically. We present the results, including a comparison to the state-of-the-art, and discuss applications for amplifiers in this frequency range. To date, these are the first cryogenic 35 nm InP MMIC results covering the 40–60 GHz range. We achieved a noise temperature less than 30 K over the 40–60 GHz range, when the amplifiers were cryogenically cooled. These results are comparable with other results in the literature, and we believe are the lowest reported for MMICs in the 50–60 GHz range.

V-band MMIC LNAs and mixers for observing the early universe

Abstract: We have developed V-Band (50–75 GHz) monolithic millimeter-wave integrated circuit (MMIC) low noise amplifiers using NGC's 35 nm InP HEMT technology. The MMIC LNAs exhibit noise temperatures of 150–270K over the full waveguide band. Subharmonic MMIC mixers were also developed using United Monolithic Semiconductor's GaAs Schottky diode process, and cover V-band with 15–21 dB conversion loss. These components form the front end of receivers that could be used for radio astronomy. While much of V-Band is opaque to the atmosphere, a future space probe to map the intensity of carbon monoxide (CO) in V-band would help astronomers understand the early universe.

Wrap around gate field effect transistor (WAGFET)

Abstract: A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.