We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.

Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

We investigate electron and hole mobilities in strained silicon nanowires (Si NWs) within an atomistic tight-binding framework. We show that the carrier mobilities in Si NWs are very responsive to strain and can be enhanced or reduced by a factor >2 (up to 5×) for moderate strains in the ±2% range. The effects of strain on the transport properties are, however, very dependent on the orientation of the nanowires. Stretched ⟨100⟩ Si NWs are found to be the best compromise for the transport of both electrons and holes in ≈10 nm diameter Si NWs. Our results demonstrate that strain engineering can be used as a very efficient booster for NW technologies and that due care must be given to process-induced strains in NW devices to achieve reproducible performances.

Effects of strain on the carrier mobility in silicon nanowires.

A simple top-down method for realizing an array of vertically stacked nanowires is presented. The process utilizes the nonuniformity in inductively coupled plasma (ICP) etching to form a scallop pattern at the sidewall of a tall silicon ridge that is further trimmed to form stacked nanowires by stress-limited oxidation. The process has been demonstrated to be controllable and repeatable, starting with bulk silicon wafers. Vertically stacked gate-all-around MOSFETs have been fabricated, which show excellent performance with a nearly ideal subthreshold slope of 62 mV/dec, a low leakage current, and a high I on/I off ratio of ~ 108.

Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.

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Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.

Programmable Resistive Device and Memory Using Diode as Selector

A method to design CMOS-compatible diode-based One-Time Programmable (OTP) memory is discussed in this paper. In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. Different memory cells were fabricated in standard 0.18-?m CMOS technology to verify the functionality of the design.

CMOS-compatible zero-mask One Time Programmable (OTP) memory design

A new method to fabricate vertically stacked single-crystal silicon nano-wires (SiNW) has been developed and presented in this work This process combines an Inductive Coupled Plasma (ICP) Dry Etch with subsequent Bosch cycle treatment followed by a one-step Self-Limiting Thermal Oxidation An N-l number of elevated SiNW cores corresponding to N Bosch cycles are experimentally demonstrated with smallest feature size down to 15 nm in diameter It is shown that the circular and elliptical eccentricity of the stacked cores can be controlled by varying the processing conditions The stress effect on the core size evolution and distribution is discussed

A New Approach to Fabricate Vertically Stacked Single-Crystalline Silicon Nanowires

A simple top down method to fabricate an array of vertically stacked nanowires is presented. By taking advantage of the non-uniformity of the Inductive Coupled Plasma (ICP) etching process to form a scalloped sidewall followed by a subsequent stress limited oxidation step, a narrow silicon fin can be vertically patterned to form stacked nanowires with different cross-sectional shapes. The stacked nanowires have been used to fabricated Gate-All-Around (GAA) MOSFETs that show excellent characteristics.

3-D matrix nano-wire transistor fabrication on silicon substrate

Microwave hydrogen plasma annealing is utilized to anneal Ti and Co films on p-type Si wafers to prepare C54 phase TiSi2 and CoSi2 at lower temperatures respectively, indicating the unstable phases are restrained in the solid state reaction due to the existence of microwave field which promotes atoms diffusion between nano-scale thickness metal film and Si substrate during anneal The method is potential to be used in nano scale devices fabrication to decrease thermal budget during IC process

Ricky M. Y. Ng

Papers

Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

CMOS-compatible zero-mask One Time Programmable (OTP) memory design

A New Approach to Fabricate Vertically Stacked Single-Crystalline Silicon Nanowires

3-D matrix nano-wire transistor fabrication on silicon substrate

Microwave plasma anneal to fabricate silicides and restrain the formation of unstable phases