Showing papers by "Robert A. Reed published in 2006"

Multiple-Bit Upset in 130 nm CMOS Technology

Abstract: The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

Implications of Nuclear Reactions for Single Event Effects Test Methods and Analysis

Abstract: Simulation results for the full galactic cosmic ray environment demonstrate that current accelerator-based test methods using linear energy transfer as the engineering metric to characterize single event effects are not sufficient to capture the nuclear reaction portion of the response. Nuclear reactions contribute significantly to on-orbit single-event rates as compared to those from direct ionization induced by the primary ions. Based on these results, the applicability of current single-event test methods to predicting on-orbit event rates is examined and improved procedures are identified. For devices with critical charge values that are in the range where nuclear reactions may play a role in determining the event rate, ground-based tests should include irradiation with several types of ions of different energies to identify the contribution of these reactions to the measured SEE cross section

Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

Abstract: Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latch-level redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity

An Investigation of Dose Rate and Source Dependent Effects in 200 GHz SiGe HBTs

Abstract: We present an investigation of the observed variations in the total dose tolerance of the emitter-base spacer and shallow trench isolation oxides in a commercial 200 GHz SiGe HBT technology. Proton, gamma, and X-ray irradiations at varying dose rates are found to produce drastically different degradation signatures at the various oxide interfaces. Extraction and analysis of the radiation-induced excess base current, as well as low-frequency noise, are used to probe the underlying physical mechanisms. Two-dimensional calibrated device simulations are employed to correlate the observed results to the spatial distributions of carrier recombination in forward- and inverse-mode operation for both pre- and post-irradiation levels. Possible explanations of our observations are offered and the implications for hardness assurance testing are discussed

Substrate Engineering Concepts to Mitigate Charge Collection in Deep Trench Isolation Technologies

Abstract: Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section

Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

Abstract: We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

SEU Error Signature Analysis of Gbit/s SiGe Logic Circuits Using a Pulsed Laser Microprobe

Abstract: We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made