An edge-sealed barrier film composite The composite includes a substrate and at least one initial barrier stack adjacent to the substrate The at least one initial barrier stack includes at least one decoupling layer and at least one barrier layer One of the barrier layers has an area greater than the area of one of the decoupling layers The decoupling layer is sealed by the first barrier layer within the area of barrier material An edge-sealed, encapsulated environmentally sensitive device is provided A method of making the edge-sealed barrier film composite is also provided

Method for edge sealing barrier films

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

The aim of the disclosed invention is to provide a capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attains extremely low resistance and low inductance involved in connection between an IC chip and the capacitor and to provide a printed wiring substrate and a capacitor used in the same. To achieve this object, a capacitor-built-in-type printed wiring substrate (100) on which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrate (110) and an IC chip (101) mounted on the capacitor-built-in-type printed wiring substrate (110). A printed wiring substrate (120) includes a number of connection-to-IC substrate bumps (152) and a closed-bottomed capacitor accommodation cavity (121) formed therein. A capacitor (130) is disposed in the cavity (121) and includes a pair of electrode groups (133E and 133F) and a number of connection-to-IC capacitor bumps (131) connected to either one of the paired electrode groups (133E and 133F). The connection-to-IC capacitor bumps (131) are flip-chip-bonded to corresponding connection-to-capacitor bumps (103) on the IC chip. The connection-to-IC substrate bumps (152) are flip-chip-bonded to corresponding connection-to-substrate bumps (104) on the IC chip.

Capacitor-built-in-type printed wiring substrate, printed wiring substrate, and capacitor

To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Electronic assemblies and systems comprising interposer with embedded capacitors

A tool for depositing multilayer coatings onto a substrate. The tool includes a housing defining a vacuum chamber connected to a vacuum source, deposition stations each configured to deposit a layer of multilayer coating on the substrate, a curing station, and a contamination reduction device. At least one of the deposition stations is configured to deposit an inorganic layer, while at least one other deposition station is configured to deposit an organic layer. In one tool configuration, the substrate may travel back and forth through the tool as many times as needed to achieve the desired number of layers of multilayer coating. In another, the tool may include numerous housings adjacently spaced such that the substrate may make a single unidirectional pass. The contamination reduction device may be configured as one or more migration control chambers about at least one of the deposition stations, and further includes cooling devices, such as chillers, to reduce the presence of vaporous layer precursors. The tool is particularly well-suited to depositing multilayer coatings onto flexible substrates, as well as to encapsulating environmentally-sensitive devices placed on the flexible substrate.

Apparatus for depositing a multilayer coating on discrete sheets

A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

High k dielectric capacitor with low k sheathed signal vias

A multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process. A method is also provided for fabricating an interposer capacitor with a multilayer ceramic substrate base and a thin film multilayer structure having at least one capacitor comprising at least one bottom platinum electrode.

High temperature, conductive thin film diffusion barrier for ceramic/metal systems

An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 μm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 μm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

Structure for a thin film multilayer capacitor

An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

Robert A. Rita

Papers

High k dielectric capacitor with low k sheathed signal vias

High temperature, conductive thin film diffusion barrier for ceramic/metal systems

Structure for a thin film multilayer capacitor

Method for a thin film multilayer capacitor

High k dielectric material with low k dielectric sheathed signal vias