J
John U. Knickerbocker
Researcher at IBM
Publications - 317
Citations - 7007
John U. Knickerbocker is an academic researcher from IBM. The author has contributed to research in topics: Wafer & Interposer. The author has an hindex of 43, co-authored 315 publications receiving 6821 citations. Previous affiliations of John U. Knickerbocker include GlobalFoundries.
Papers
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Journal ArticleDOI
Three-dimensional silicon integration
John U. Knickerbocker,P.S. Andry,B. Dang,R. Horton,Mario J. Interrante,Chirag S. Patel,Robert J. Polastre,Katsuyuki Sakuma,R. Sirdeshmukh,Edmund J. Sprogis,Sri M. Sri-Jayantha,A. M. Stephens,Anna W. Topol,Cornelia K. Tsang,B. C. Webb,Steven L. Wright +15 more
TL;DR: 3D technology from IBM is highlighted, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and examples of 3D emerging industry product applications that could create marketable systems are provided.
Journal ArticleDOI
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
John U. Knickerbocker,P.S. Andry,Leena Paivikki Buchwalter,Alina Deutsch,R. Horton,Keith A. Jenkins,Young H. Kwark,Gerard McVicker,Chirag S. Patel,Robert J. Polastre,Christian Schuster,Arun Sharma,Sri M. Sri-Jayantha,C.W. Surovic,Cornelia K. Tsang,Bucknell C. Webb,Steven L. Wright,Samuel McKnight,Edmund J. Sprogis,B. Dang +19 more
TL;DR: The technical challenges and recent progress made in the development of silicon carrier technology for potential new applications are described.
Proceedings ArticleDOI
3D silicon integration
John U. Knickerbocker,P.S. Andry,B. Dang,R. Horton,Chirag S. Patel,Robert J. Polastre,Katsuyuki Sakuma,E.S. Sprogis,Cornelia K. Tsang,B. C. Webb,Steven L. Wright +10 more
TL;DR: In this article, the authors describe recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures, as well as examples of potential applications that may take advantage of 3D integration are discussed.
Journal ArticleDOI
An overview of through-silicon-via technology and manufacturing challenges
TL;DR: A comprehensive overview of through-silicon-via technology (TSV) is presented, including etch, insulation, and metallization, along with the backside processing, assembly, metrology, design, packaging, reliability, testing and yield challenges that arise with the use of TSVs.
Journal ArticleDOI
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
John U. Knickerbocker,Chirag S. Patel,P.S. Andry,Cornelia K. Tsang,Leena Paivikki Buchwalter,Edmund J. Sprogis,Hua Gan,R. Horton,Robert J. Polastre,Steven L. Wright,John M. Cotte +10 more
TL;DR: In this article, the authors discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example, and discuss a silicon carrier package technology with fine pitch (50 mum) interconnection.