A computer system has one or more software context that share use of a memory that is divided into units such as pages In the preferred embodiment of the invention, the context are, or include, virtual machines running on a common hardware platform The context, as opposed to merely the addresses or page numbers, of virtual memory pages that accessible to one or more contexts are examined If two or more context pages are identical, then their memory mappings are changed to point to a single, shared copy of the page in the hardware memory, thereby freeing the memory space taken up by the redundant copies The shared copy is ten preferable marked copy-on-write Sharing is preferably dynamic, whereby the presence of redundant copies of pages is preferably determined by hashing page contents and performing full content comparisons only when two or more pages hash to the same key

Content-based, transparent sharing of memory units

Table data is stored by parsing the table data into columns of values, formatting each column into a data stream, and transferring each data stream to a storage device for storage as a continuous strip of data The strip of data is stored as a file that is not structured as a series of pages The formatting of the data stream may include compressing the column values to minimize the length of the data strip A particular compression procedure may be used that derives a code for each value in the column from a number of occurrences of the value in the column and replaces the value in the data stream with the corresponding code

Storage of row-column data

A multi-threaded microprocessor (1105) for processing instructions in threads The microprocessor (1105) includes first and second decode pipelines (17300, 17301), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (17300, 17301) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750) Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed

Improved multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture

A processor (300) includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition The procesor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers

Switching method in a multi-threaded processor

A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

Storage device and information processing system

A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.

Cache management for a multi-threaded processor

A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.

Method and system allowing a single entity to manage memory comprising compressed and uncompressed data

The present invention, in various embodiments, provides techniques for managing latencies in accessing memory of computer systems. In one embodiment, upon accessing the memory system for a piece of data used by a first process, a latency manager determines the access time to acquire the piece of data in the memory system. The latency manager then compares the determined access time to a threshold. If the determined access time is greater than the threshold, the latency manager triggers an interrupt for the operating system to switch threads or processes so that execution of the first process is postponed and execution of a second process starts. Various embodiments include the latency manager is polled for the access time when the processor is stalled, the latency manager triggers a process switch when a particular memory subsystem is accessed, etc.

Managing latencies in accessing memory of computer systems

A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory

A method for inline bus data compression and decompression is disclosed. In one embodiment, data is selected for transfer via a data bus, the data is divided into byte sized divisions of the bus width, and each byte is compressed by an individual compression engine. The data is then properly sequenced, aligned and recombined and further transmitted in its compressed state. When required to be decompressed, the compressed data is again divided into bytes of compressed data, each byte being decompressed individually, and then restored to the bus in its uncompressed form, in essence, in the reverse order of the compression process.

Robert Bruce Aglietti

Papers

Cache management for a multi-threaded processor

Method and system allowing a single entity to manage memory comprising compressed and uncompressed data

Managing latencies in accessing memory of computer systems

Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory

Method for improving inline compression bandwidth for high speed buses