Patent
Cache management for a multi-threaded processor
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TLDR
In this paper, the cache memory is partitioned among a set of threads of a multi-threaded processor, and when a cache miss occurs, a replacement line is selected in a partition of the cache space which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.Abstract:
A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.read more
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Improved multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
TL;DR: A multi-threaded microprocessor (1105) for processing instructions in threads is described in this article, which includes first and second decode pipelines (17300, 17301), first andsecond execute pipelines ( 1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and two threads from the first and first decode pipelines, respectively, to the first or second execute pipelines.
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Switching method in a multi-threaded processor
TL;DR: A processor (300) includes logic for attaining very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition.
Patent
Buffer memory management in a system having multiple execution entities
Zhong-ning Cai,Tosaku Nakanishi +1 more
TL;DR: In this article, an instruction of one of the execution entities is retrieved and an associated identifier is decoded and information associated with the instruction is stored in a cache section based on the identifier.
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Multiple-thread processor with single-thread interface shared among threads
TL;DR: In this article, a technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits, which can be inserted at the most significant bits of the cache index.
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Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
John R. Nickolls,Stephen D. Lew +1 more
TL;DR: In this article, the authors present a mechanism for loading and launching cooperative thread arrays (CTAs) in a representative processing core and for synchronizing threads within a CTA, respectively.
References
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Patent
Multi-threaded microprocessor architecture utilizing static interleaving
Jin-Chin Chung,Chuan-Lin Wu +1 more
TL;DR: In this paper, a static interleaving technique is proposed to solve the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture, where each function unit in the processor is allocated for the execution of an instruction from a particular thread in a fixed predetermined time slot in a repeating pattern of predetermined time slots.
Patent
Computer system with private and shared partitions in cache
Abstract: The traditional computer system is modified by providing, in addition to a processor unit, a main memory and a cache memory buffer, remapping logic for remapping the cache memory buffer, and a plurality of registers for containing remapping information. With this environment the cache memory buffer is divided into segments, and the segments are one or more cache lines allocated to a task to form a partition, so as to make available (if a size is set above zero) of a shared partition and a group of private partitions. Registers include the functions of count registers which contain count information for the number of cache segments in a specific partition, a flag register, and two register which act as cache identification number registers. The flag register has bits acting as a flag, which bits include a non-real time flag which allows operation without the partition system, a private partition permitted flag, and a private partition selected flag. With this system a traditional computer system can be changed to operate without impediments of interrupts and other prior impediments to a real-time task to perform. By providing cache partition areas, and causing an active task to always have a pointer to a private partition, and a size register to specify how many segments can be used by the task, real time systems can take advantage of a cache. Thus each task can make use of a shared partition, and know how many segments can be used by the task. The system cache provides a high speed access path to memory data, so that during execution of a task the logic means and registers provide any necessary cache partitioning to assure a preempted task that it's cache contents will not be destroyed by a preempting task. This permits use of a software controlled partitioning system which allows segments of a cache to be statically allocated on a priority I benefit basis without hardware modification to said system. The cache allocation provided by the logic gives consideration of the scheduling requirements of tasks of the system in deciding the size of each cache partition. Accordingly, the cache can make use of a for dynamic programming implementation of an allocation algorithm which can determine an optimal cache allocation in polynomial time.
Patent
Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers
TL;DR: In this paper, a data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers and masquerade registers, pipeline controller, a memory controller and a pair of internal buses.
Patent
Scoreboard for cached multi-thread processes
TL;DR: In this article, the scheduler algorithm of the computer operating system determines the most advantageous order for the process threads to run and which of the processors in a multi-processor system should execute these process threads.
Patent
Maximal concurrent lookup cache for computing systems having a multi-threaded environment
Thomas K. Wong,Theron D. Tock +1 more
TL;DR: In this article, the location in the cache of an item that includes a first key is determined by supplying the first key to a lockless-lookup engine which then provides a lookup output that is alternatively a lookup entry number or an indication that the item is not stored in cache.