A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Phase shifting circuit manufacture method and apparatus

In this thesis, we first look at the Optical Proximity Correction (OPC) problem and define the goals, constraints, and techniques available. Then, a practical and general OPC framework is built up using concepts from linear systems, control theory, and computational geometry. A simulation-based, or model-based, OPC algorithm is developed which simulates the optics and processing steps of lithography for millions of locations. The key contributions to the OPC field made in this thesis work include: (1) formulation of OPC as a feedback control problem using an iterative solution, (2) an algorithm for edge movement during OPC with cost function criteria, (3) use of fast aerial image simulation for OPC, which truly enables full chip model-based OPC, and (4) the variable threshold resist (VTR) model for simplified prediction of CD based off aerial image.
A major contribution of this thesis is the development of a fast aerial image simulator which is tailored to the problem of OPC. In OPC applications, it is best to compute intensity at sparse points. Therefore, our fast aerial image simulator is tailored to computing intensity at sparse points, rather than on a regular dense grid. The starting point for the fast simulation is an established decomposition of the Hopkins partially coherent imaging equations, originally proposed by Gamo (14). Within this thesis, the decomposition is called the Sum of Coherent Systems (SOCS) structure. The numerical implementation of this decomposition using Singular Value Decomposition (SVD) is described in detail.
Another contribution of this thesis is the development of a variable threshold resist model (VTR). The model uses the aerial image peak intensity and image slope along a cutline to deduce the development point of the resist, and has two primary benefits: (1) it is fast, (2) it can be fit to empirical data.
We combine the fast aerial image simulator and the VTR model in an iterative feedback loop to formulate OPC as a feedback control problem. (Abstract shortened by UMI.)

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Fast optical and process proximity correction algorithms for integrated circuit manufacturing

Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user. The appropriate layout processing actions are applied to matching portions of the IC layout to form the corrected photomask layout. This process can be sequential or batch mode. Shape and action conflicts can be resolved by marking identified/modified elements or by designing rules for orderly resolution of any inconsistencies or overlaps.

General purpose shape-based layout processing scheme for IC layout modifications

Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Dissection of printed edges from a fabrication layout for correcting proximity effects

Fast lithography simulation and its use in optical proximity correction (OPC) is the topic of this paper. We summarize a model-based OPC system which uses simulation in a feedback loop to generate corrections to the mask. At the heart of our OPC system are tools for fast simulation of the optical and process physics of lithography. For image simulation, we apply a sum of coherent systems approximation to Hopkins partial coherence model and then use lookup tables for high speed sparse image simulation over arbitrary mask geometry. Image intensity simulation at a single point is achieved with O(Me) computation where Me is the number of polygon edges in a region surrounding the point. This allows more than 10,000 aerial image points per second and mask image perturbation speeds of 51,000 points per second on an HP700 workstation. A simplified physically based, empirically parameterized resist model is then used to determine edge placements, given the image intensity samples. Together, these systems make up a 'process-tuned' simulation model which can be used for OPC. The accuracy of the overall model is shown by comparing to empirical measurement data. By integrating the fast simulation tools with our OPC system, we can correct a 48 X 27 micrometers 2 area in 6 iterations at 96 sec/iteration.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Mathematical and CAD framework for proximity correction

Proximity effect correction presumes that a significant proportion of CD variations observed in wafer lithography and processes can be systematically predicted from calculations made on a pattern layout prior to fabrication. Total shape variations include a portion that repeats from chip-to-chip and wafer-to-wafer, and a randomly varying portion. Repeating effects can be compensated by modifying feature shapes on the mask pattern. The project described in this report is a study to characterize the systematic shape distortions in an experimental 0.25 micrometers process. Analyses of variation are made to quantify dependencies on specific variation sources. Two-dimensional 'behavior models,' derived from characterization data measured from processed wafers, can be used to compute shape corrections for arbitrary pattern layouts. This project was undertaken in collaboration with the Hewlett Packard Research Laboratories, Palo Alto, CA.

Quantifying proximity and related effects in advanced wafer processes

We have developed a method for patterning sub-micrometer gates with T-shaped cross sections, which may be applied to manufacture high performance field effect transistors (FETs). The technique employs two exposures at the KrF excimer laser wavelength (248 nm). The first exposure uses a phase-shifting mask to pattern 0.1 micrometers isolated spaces. The resist used for the second exposure absorbs the 248 nm radiation strongly enough to produce a profile suitable for lift-off patterning.

Fabrication of 0.1-um T-shaped gates by phase-shifting optical lithography

We have studied systematic line width (CD) errors as functions of field coordinates for three late-model i-line steppers from different manufacturers by measuring electrical resistance of lines patterned in poly-silicon. The combination of reticle errors with non-linear imaging accounts for a significant fraction of the total line width errors. After removing the effects of reticle errors, CD contour maps are consistent with aberration patterns in which the Strehl intensity is highest at the center of the field.

Contributions of stepper lenses to systematic CD errors within exposure fields

A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor is conducting, thereby insuring maximum voltage swing of the output voltage. The circuit means comprises an MOS transistor for discharging the base of an output transistor, and a depletion mode MOS transistor for connecting the base of an output transistor to its emitter. By utilizing MOS and depletion mode transistors, a significant area advantage is achieved, particularly when the MOS and depletion mode transistors are merged.

BICMOS logic gate with higher pull-up voltage

We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.

Robert E. Gleason

Papers

Quantifying proximity and related effects in advanced wafer processes

Fabrication of 0.1-um T-shaped gates by phase-shifting optical lithography

Contributions of stepper lenses to systematic CD errors within exposure fields

BICMOS logic gate with higher pull-up voltage

100-nm CMOS gates patterned with 3 sigma below 10 nm