An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A new method for CVD deposition on a substrate is taught wherein radical species are used in alternate steps to depositions from a molecular precursor to treat the material deposited from the molecular precursor and to prepare the substrate surface with a reactive chemical in preparation for the next molecular precursor step. By repetitive cycles a composite integrated film is produced. In a preferred embodiment the depositions from the molecular precursor are metals, and the radicals in the alternate steps are used to remove ligands left from the metal precursor reactions, and to oxidize or nitridize the metal surface in subsequent layers. A variety of alternative chemistries are taught for different films, and hardware combinations to practice the invention are taught as well.

Radical-assisted sequential CVD

Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

Conformal thin films over textured capacitor electrodes

A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a high dielectric constant oxide (40) on the seed layer (20;20').

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

A method and apparatus for performing atomic layer deposition in which a surface of a substrate is pretreated to make the surface of the substrate reactive for performing atomic layer deposition.

Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition

Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.

Integrated circuit capacitor

Leakage and breakdown characteristics of low-k dielectrics are becoming increasingly important reliability issues for interconnects as they are scaled to 0.18 um and below. Several of the low-k dielectrics, integrated into a dual-damascene Cu process flow, are quite leaky and have difficulty in meeting a leakage spec of 1E-8 A/cm/sup 2/ at 25/spl deg/C. Time-dependent dielectric breakdown (TDDB) for some of the low-k candidate films is also an issue because of generally low breakdown strengths <2 MV/cm. Furthermore, Cu out-diffusion through poor barrier confinement can result in increased electronic leakage and premature TDDB. Also, moisture absorption by these low-k materials serves to: increase the dielectric constant, increase the leakage and reduce the breakdown strength. These findings can have important reliability implications for Cu/low-k and care must be exercised in dual-damascene integration schemes.

Leakage and breakdown reliability issues associated with low-k dielectrics in a dual-damascene Cu process

A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size. including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.

Method of making barium strontium titanate (BST) thin film by erbium donor doping

Scanning tunneling microscopy has been employed to study the adsorption of disilane (${\mathrm{Si}}_{2}$${\mathrm{H}}_{6}$) and pyrolytic growth on Si(100)-(2\ifmmode\times\else\texttimes\fi{}1) at various temperatures. Room-temperature exposures result in a random distribution of dissociation fragments on the surface. Formation of anisotropic monohydride islands and denuded zones as well as island coarsening is observed at higher temperatures. The results are strikingly similar to those reported for growth by molecular-beam epitaxy using pure Si, even though different surface reactions are involved in these two growth processes.

Scanning-tunneling-microscopy studies of disilane adsorption and pyrolytic growth on Si(100)-(2x1).

Current flow through Pt/(Ba0.7Sr0.3)TiO3/Pt stack consists of both polarization current and electronic leakage current, which were separated by monitoring the discharging current when applied voltage was turned off. Electronic current comes from electrical field enhanced Schottky emission at the electrode–dielectric interface, and dominates the current flow at high electric field. At low electric field, polarization current prevails. The voltage and time dependence of the polarization current can be modeled by a distribution of Debye‐type relaxations. The relaxation time and capacitance derived from current–time measurements were applied to simulate the current–voltage behavior, where good fitting to experimental result was obtained.

Robert Tsu

Papers

Integrated circuit capacitor

Leakage and breakdown reliability issues associated with low-k dielectrics in a dual-damascene Cu process

Method of making barium strontium titanate (BST) thin film by erbium donor doping

Scanning-tunneling-microscopy studies of disilane adsorption and pyrolytic growth on Si(100)-(2x1).

Direct current conduction properties of sputtered Pt/(Ba0.7Sr0.3)TiO3/Pt thin films capacitors