R
Roshan Ragel
Researcher at University of Peradeniya
Publications - 153
Citations - 1203
Roshan Ragel is an academic researcher from University of Peradeniya. The author has contributed to research in topics: Encryption & Side channel attack. The author has an hindex of 17, co-authored 152 publications receiving 977 citations. Previous affiliations of Roshan Ragel include University of Southampton & University of New South Wales.
Papers
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Journal ArticleDOI
Processor Design for Soft Errors: Challenges and State of the Art
TL;DR: This article introduces the soft error problem from the perspective of processor design and provides a survey of the existing soft error mitigation methods across different levels of design abstraction involved in processor design, including the devicelevel, the circuit level, the architectural level, and the program level.
Proceedings ArticleDOI
RIJID: random code injection to mask power analysis based side channel attacks
TL;DR: A HW/SW based randomized instruction injection technique is proposed in this paper to overcome the pitfalls of previous countermeasures and injects random instructions at random places during the execution of an application which protects the system from both SPA and DPA.
Proceedings ArticleDOI
IMPRES: integrated monitoring for processor reliability and security
Roshan Ragel,Sri Parameswaran +1 more
TL;DR: This paper presents a novel hardware/software technique at the granularity of micro-instructions to reduce overheads considerably and shows that these overheads are far smaller than have been previously encountered.
Journal ArticleDOI
An Ensemble Learning Approach for Electrocardiogram Sensor Based Human Emotion Recognition
TL;DR: This research suggests an ensemble learning approach for developing a machine learning model that can recognize four major human emotions namely: anger; sadness; joy; and pleasure incorporating electrocardiogram (ECG) signals.
Proceedings ArticleDOI
A smart random code injection to mask power analysis based side channel attacks
TL;DR: This paper shows a processor architecture, which automatically detects the execution of the most common encryption algorithms, starts to scramble the power waveform by adding randomly placed instructions with random register accesses, and stops injecting instructions when it is safe to do so, and has less overheads compared to previous solutions and avoids software instrumentation.