Ross Daly

TL;DR: This paper exposes the vulnerability of commodity DRAM chips to disturbance errors, and shows that it is possible to corrupt data in nearby addresses by reading from the same address in DRAM by activating the same row inDRAM.

TL;DR: This paper presents Rigel, which takes pipelines specified in the new multi-rate architecture and lowers them to FPGA implementations, and demonstrates depth from stereo, Lucas-Kanade, the SIFT descriptor, and a Gaussian pyramid running on two FPGAs.

TL;DR: CoSA (CoreIR Symbolic Analyzer), a model-checking tool for CoreIR designs, which natively supports encodings using the theories of bitvectors and arrays and provides a broad set of analyses including equivalence checking and safety and liveness verification.

TL;DR: A system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits, and a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput are described.

TL;DR: This work provides a systematic approach for desiging and evolving high-performance and energy-efficient hardware-software systems for any application domain with DSL-based hardware generators that provide the Verilog needed for the implementation of the CGRA.